SHF: Small: Minimizing System Level Testing of Processor SOCs

集成电路（ic）和更复杂的片上系统（soc）是所有现代计算和通信系统（从手机到云计算系统）的核心。在这些复杂的电子部件中，数十亿个单独的电路元件被集成在不到一平方英寸的硅上。不幸的是，这种微观组件容易受到制造缺陷和变化的影响，这些缺陷和变化会严重影响集成电路的性能和可靠性。该项目旨在显著改善集成电路的制造后测试，以便在组装成更大的最终用途设备和系统之前可靠地检测和筛选缺陷和边缘部件。目标是降低制造成本，提高电子系统的可靠性。更广泛地说，该项目有望加强奥本大学的教育和研究项目，并为阿拉巴马州和全国不断发展的电子、汽车和航空航天工业提供工程人才储备。传统上，开发集成电路的电气制造后测试是为了检查可能制造故障的目标列表上的不同可能故障情况。测试使用集成电路在几秒钟内排除几乎所有目标故障的存在。不幸的是，越来越多的人观察到，这种有针对性的测试未能捕捉到许多最终出现在组装系统中的故障部件。因此，工业界被迫引入一种新型的测试，即在实际功能操作中广泛测试新制造的集成电路，通常至少10到15分钟，以检查其功能是否完全正确。这些新的系统级测试（slt）显著增加了测试成本。该项目正在研究一种创新的自适应方法，通过避免大部分制造ic的SLT来最大限度地降低成本。这是通过使用创新的预测方法（包括机器学习），根据现有的传统测试结果，准确预测每个IC失败SLT的可能性来实现的。预计对于超过一半的制造部件，这种可能性将足够小，IC可以跳过SLT，而不会在材料上降低整个系统的可靠性，从而显著节省测试成本。该奖项反映了美国国家科学基金会的法定使命，并通过使用基金会的知识价值和更广泛的影响审查标准进行评估，被认为值得支持。

Integrated circuits (ICs), and more complex Systems-on-Chip (SOCs), are at the heart of all modern computing and communication systems, ranging from cell phones to cloud computing systems. In these complex electronic parts, billions of individual circuit components are incorporated on less than a square inch of silicon. Unfortunately, such microscopic components are subject to manufacturing defects and variations that can significantly impact the performance and dependability of the IC. This project aims at significantly improving the post manufacturing testing of ICs to reliably detect and screen out defective and marginal parts before they are assembled into larger end-use devices and systems. The goal is to reduce manufacturing costs and increase the reliability of electronic systems. More broadly, the project is expected to strengthen the educational and research programs at Auburn University, and enhance the pool of engineering talent available to the growing electronics, automotive and aerospace industries in Alabama, and the nation.Traditionally, electrical post manufacturing tests for ICs are developed to check for the different possible failure scenarios on a target list of likely manufacturing faults. The tests exercise the IC to rule out the existence of nearly all the targeted failures within just a few seconds. Unfortunately, it has been increasingly observed that such targeted tests fail to catch many malfunctioning parts that end up in assembled systems. Consequently, industry has been forced to introduce a new type of test that extensively exercises newly manufactured ICs in actual functional operation for sufficiently long, usually at least ten to fifteen minutes, to check for fully correct functioning. These new System Level Tests (SLTs) significantly increase test cost. This project is investigating an innovative adaptive approach for minimizing costs by avoiding SLT for a significant fraction of the manufactured ICs. This is achieved by accurately predicting the likelihood of each IC failing SLT based on available traditional test results, using innovative prediction methods, including machine learning. It is expected that for more than half the manufactured parts, this probability will be small enough for the IC to skip SLT without materially degrading overall system reliability, thereby resulting in significant test cost savings.This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.