SHF: Small: Minimizing System Level Testing of Processor SOCs

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Integrated circuits (ICs), and more complex Systems-on-Chip (SOCs), are at the heart of all modern computing and communication systems, ranging from cell phones to cloud computing systems. In these complex electronic parts, billions of individual circuit components are incorporated on less than a square inch of silicon. Unfortunately, such microscopic components are subject to manufacturing defects and variations that can significantly impact the performance and dependability of the IC. This project aims at significantly improving the post manufacturing testing of ICs to reliably detect and screen out defective and marginal parts before they are assembled into larger end-use devices and systems. The goal is to reduce manufacturing costs and increase the reliability of electronic systems. More broadly, the project is expected to strengthen the educational and research programs at Auburn University, and enhance the pool of engineering talent available to the growing electronics, automotive and aerospace industries in Alabama, and the nation.Traditionally, electrical post manufacturing tests for ICs are developed to check for the different possible failure scenarios on a target list of likely manufacturing faults. The tests exercise the IC to rule out the existence of nearly all the targeted failures within just a few seconds. Unfortunately, it has been increasingly observed that such targeted tests fail to catch many malfunctioning parts that end up in assembled systems. Consequently, industry has been forced to introduce a new type of test that extensively exercises newly manufactured ICs in actual functional operation for sufficiently long, usually at least ten to fifteen minutes, to check for fully correct functioning. These new System Level Tests (SLTs) significantly increase test cost. This project is investigating an innovative adaptive approach for minimizing costs by avoiding SLT for a significant fraction of the manufactured ICs. This is achieved by accurately predicting the likelihood of each IC failing SLT based on available traditional test results, using innovative prediction methods, including machine learning. It is expected that for more than half the manufactured parts, this probability will be small enough for the IC to skip SLT without materially degrading overall system reliability, thereby resulting in significant test cost savings.This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.