Research Initiation: Fault Tolerance Schemes for High Performance WSI Processor Arrays

正在为非常高性能的处理器阵列开发面积高效、容错的晶片级集成架构，以特别确保重组后的短而有限的互连长度。正在开发新的产量和性能模型，以现实地评估这些设计。用于矩阵乘法的半导体芯片正通过MOSIS(金属氧化物半导体实现系统)设施实现。预计性能接近10亿次浮点运算。晶片规模的集成允许开发高性能的处理器。在这种设计中，处理器间信号不受芯片外传播延迟的影响。容错问题在这种设计中尤其重要，以克服由于制造缺陷而导致的重新配置造成的长时间延迟。

The development of area efficient fault-tolerant wafer-scale integration architectures for very high performance processor arrays that specifically ensure short and bounded interconnection lengths following restructuring is being carried out. New yield and performance models to realistically evaluate the designs are being developed. Semiconductor chips for matrix multiplication are being implemented through the MOSIS (Metal Oxide Semiconductor Implementation System) facility. Performance approaching one billion floating point operations is expected. Wafer-scale integration allows processors of high performance to be developed. In such designs, interprocessor signals are not subject to off-chip propagation delays. Issues on fault tolerance are especially important in such designs in order to overcome long delays caused by reconfiguration due to fabrication defects.