Research Initiation: Fault Tolerance Schemes for High Performance WSI Processor Arrays

用于高性能处理器阵列的区域高效容错晶圆级集成架构的开发正在进行，特别是确保重构后的短而有限的互连长度。新的良率和性能模型正在开发中，以实际评估设计。用于矩阵乘法的半导体芯片正在通过MOSIS（金属氧化物半导体实现系统）设施实现。预计性能将接近10亿次浮点运算。晶圆级集成允许开发高性能处理器。在这样的设计中，处理器间信号不受片外传播延迟的影响。为了克服由于制造缺陷引起的重构所造成的长时间延迟，容错问题在此类设计中尤为重要。

The development of area efficient fault-tolerant wafer-scale integration architectures for very high performance processor arrays that specifically ensure short and bounded interconnection lengths following restructuring is being carried out. New yield and performance models to realistically evaluate the designs are being developed. Semiconductor chips for matrix multiplication are being implemented through the MOSIS (Metal Oxide Semiconductor Implementation System) facility. Performance approaching one billion floating point operations is expected. Wafer-scale integration allows processors of high performance to be developed. In such designs, interprocessor signals are not subject to off-chip propagation delays. Issues on fault tolerance are especially important in such designs in order to overcome long delays caused by reconfiguration due to fabrication defects.