Research Initiation: Fault Tolerance Schemes for High Performance WSI Processor Arrays

面积有效的容错晶圆级芯片的研制 超高性能处理器集成结构 专门确保短和有界互连的阵列 重组后的长度正在进行。 新收益率 和性能模型来实际评估设计， 正在开发中。 矩阵乘法用半导体芯片 正在通过MOSIS（金属氧化物 半导体实现系统）设施。 性能 预计接近十亿次浮点运算。 晶圆级集成使高性能处理器能够 发展。在这样的设计中，处理器间信号不被 受到芯片外传播延迟影响。 过错问题 公差在这种设计中特别重要， 克服由于制造而重新配置所引起的长延迟 缺陷

The development of area efficient fault-tolerant wafer-scale integration architectures for very high performance processor arrays that specifically ensure short and bounded interconnection lengths following restructuring is being carried out. New yield and performance models to realistically evaluate the designs are being developed. Semiconductor chips for matrix multiplication are being implemented through the MOSIS (Metal Oxide Semiconductor Implementation System) facility. Performance approaching one billion floating point operations is expected. Wafer-scale integration allows processors of high performance to be developed. In such designs, interprocessor signals are not subject to off-chip propagation delays. Issues on fault tolerance are especially important in such designs in order to overcome long delays caused by reconfiguration due to fabrication defects.