Exploiting Defect Clustering Information in VLSI Testing
在 VLSI 测试中利用缺陷聚类信息
基本信息
- 批准号:9208929
- 负责人:
- 金额:$ 14.01万
- 依托单位:
- 依托单位国家:美国
- 项目类别:Standard Grant
- 财政年份:1992
- 资助国家:美国
- 起止时间:1992-10-01 至 1996-03-31
- 项目状态:已结题
- 来源:
- 关键词:
项目摘要
This project is investigating the use of information about defect clustering on wafers to make yield predictions for individual dies based on test results for neighboring dies. The hypothesis is that defects on a wafer are clustered, thus most good dies are close to other good ones and most defective dies are close to others. Clustering information can then be used for targeting particular tests to individual dies on the wafer. Simulations using wafer defect distribution data from the published literature is being employed to assess the viability of the approach. Accurate models to predict defect levels attainable are being developed and strategies for testing dies on the wafer are being determined.
该项目正在研究如何利用晶圆上缺陷聚集的信息,根据相邻芯片的测试结果来预测单个芯片的良率。 假设晶圆上的缺陷是聚集的,因此大多数好的芯片与其他好的芯片接近,而大多数有缺陷的芯片与其他芯片接近。 然后,聚类信息可用于针对晶圆上的各个芯片进行特定测试。 使用已发表文献中的晶圆缺陷分布数据进行模拟来评估该方法的可行性。 正在开发预测可达到的缺陷水平的准确模型,并确定测试晶圆上芯片的策略。
项目成果
期刊论文数量(0)
专著数量(0)
科研奖励数量(0)
会议论文数量(0)
专利数量(0)
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Adit Singh其他文献
Adit Singh的其他文献
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{{ truncateString('Adit Singh', 18)}}的其他基金
Collaborative Research: An Effective and Efficient Low-Cost Alternate to Cell Aware Test Generation for Cell Internal Defects
协作研究:针对电池内部缺陷的电池感知测试生成有效且高效的低成本替代方案
- 批准号:
2331003 - 财政年份:2023
- 资助金额:
$ 14.01万 - 项目类别:
Standard Grant
SHF: Small: Minimizing System Level Testing of Processor SOCs
SHF:小型:最大限度地减少处理器 SOC 的系统级测试
- 批准号:
1910964 - 财政年份:2019
- 资助金额:
$ 14.01万 - 项目类别:
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SHF: Small: Targeting Hazard Activated Faults to Improve Open Defect Coverage of Scan Delay Tests
SHF:小型:针对危险激活的故障以提高扫描延迟测试的开放缺陷覆盖率
- 批准号:
1527049 - 财政年份:2015
- 资助金额:
$ 14.01万 - 项目类别:
Standard Grant
COLLABORATIVE RESEARCH: TIMING VARIATION RESILIENT SIGNAL PROCESSING: HARDWARE-ASSISTED CROSS-LAYER ADAPTATION
合作研究:时序变化弹性信号处理:硬件辅助跨层自适应
- 批准号:
1319529 - 财政年份:2013
- 资助金额:
$ 14.01万 - 项目类别:
Standard Grant
Collaborative Research: Targeting Multi-Core Clock Performance Gains in the face of Extreme Process Variations
协作研究:面对极端的工艺变化,瞄准多核时钟性能增益
- 批准号:
0903449 - 财政年份:2009
- 资助金额:
$ 14.01万 - 项目类别:
Standard Grant
Silicon Calibrated Scan Based Timing Tests for Delay Defect Detection
用于延迟缺陷检测的基于硅校准扫描的时序测试
- 批准号:
0811454 - 财政年份:2008
- 资助金额:
$ 14.01万 - 项目类别:
Standard Grant
EHCS: Dynamic Vertically Integrated Power-Performance-Reliability Modulation in Embedded Digital Signal Processors
EHCS:嵌入式数字信号处理器中的动态垂直集成功率性能可靠性调制
- 批准号:
0834620 - 财政年份:2008
- 资助金额:
$ 14.01万 - 项目类别:
Continuing Grant
ITR: Built-In Test of High Speed/RF Mixed Signal Electronics
ITR:高速/射频混合信号电子设备的内置测试
- 批准号:
0325426 - 财政年份:2003
- 资助金额:
$ 14.01万 - 项目类别:
Continuing Grant
Wafer Oriented Trend Analysis for VLSI Test Opitmazation
面向晶圆的趋势分析,用于 VLSI 测试优化
- 批准号:
9912389 - 财政年份:2000
- 资助金额:
$ 14.01万 - 项目类别:
Continuing Grant
Research Initiation: Fault Tolerance Schemes for High Performance WSI Processor Arrays
研究启动:高性能WSI处理器阵列的容错方案
- 批准号:
8808325 - 财政年份:1988
- 资助金额:
$ 14.01万 - 项目类别:
Standard Grant
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