Wafer Oriented Trend Analysis for VLSI Test Opitmazation

点击翻译按钮获取中文摘要

The mainstream approach to improving the quality of IC testing is to develop better tests that target more realistic failure mechanisms. This project is investigating an orthogonal approach that promises significant improvements in the effectiveness of any given testing procedure by employing wafer based spatial test information as additional input in interpreting test results. This spatial information is useful in making the best possible judgement about circuit quality because of the widely observed clustering of defects on semiconductor wafers, and the fact that circuit parameters track closely for adjacent dice on the same wafer. Early results indicate the potential for defect level improvements up to an order of magnitude in screening for high quality circuits, and the possibility of screening out potential early-life failures, without expensive burn-in tests. On-going research aims at validating these findings on new, more voluminous, industrial test data, and also developing analytical models to estimate the test quality improvements. The new approach is also being investigated for developing neighborhood-based thresholds for optimally interpreting test results in non-Boolean test approaches, such as IDDQ and very low voltage testing.