Collaborative Research: Targeting Multi-Core Clock Performance Gains in the face of Extreme Process Variations

协作研究：面对极端的工艺变化，瞄准多核时钟性能增益

• 批准号: 0903449
• 负责人: Adit Singh
• 金额: $ 15.38万
• 依托单位: Auburn University
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2009
• 资助国家: 美国
• 起止时间: 2009-09-15 至 2013-08-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=0903449&HistoricalAwards=false
• 关键词: Collaborative; Research; Targeting; Multi; Core

The objective of this research is to overcome barriers limiting multicore processor clock frequencies and to achieve faster clock and data throughput rates with technology scaling than currently possible. The approach is to design hardware and software infrastructure into multicore processors that enables low cost comparison testing of the individual processor cores and test driven tuning of processor circuitry for high-speed core operation. The intellectual merit of this work lies in the ability of the underlying test and adaptation algorithms to extract the maximum amount of performance from the process cores that they are capable of delivering under inter and intra die process variations and electrical field degradation. Such adaptation is achieved with limited test and diagnosis cost while allowing possible "test escapes" to be handled in a fail-safe manner that does not result in a system crash. The diagnostics information generated is used to tune individual processor core circuitry for speed purposes. The broader impacts of this research include the ability to run advanced applications on multicore processors in, for example, future 4G mobile wireless systems including high definition video, interactive displays, image processing, data mining algorithms and other pervasive computing tasks that demand high processor throughput at low power for low heat dissipation and high device reliability. The project will also enable training of students and industry personnel in a new interdisciplinary field that involves fundamental concepts from electrical engineering, device physics and computer science through prototype demonstrations, seminars, workshops, cooperative research and student internships in industry.

本研究的目的是克服限制多核处理器时钟频率的障碍，并实现更快的时钟和数据吞吐率与技术扩展比目前可能的。该方法是将硬件和软件基础设施设计到多核处理器中，从而实现对各个处理器内核的低成本比较测试以及对处理器电路的测试驱动调优以实现高速内核操作。这项工作的智力价值在于底层测试和自适应算法的能力，以提取最大量的性能，他们能够在芯片间和芯片内工艺变化和电场退化下提供的工艺核心。这样的适应是以有限的测试和诊断成本实现的，同时允许以不会导致系统崩溃的故障安全方式处理可能的“测试逃逸”。 所生成的诊断信息用于调整单个处理器内核电路，以提高速度。这项研究的更广泛的影响包括在多核处理器上运行高级应用的能力，例如，未来的4G移动的无线系统，包括高清视频、交互式显示、图像处理、数据挖掘算法和其他普及计算任务，这些任务需要低功耗的高处理器吞吐量，以实现低散热和高设备可靠性。该项目还将通过原型演示、研讨会、讲习班、合作研究和学生工业实习，在一个新的跨学科领域培训学生和工业人员，该领域涉及电气工程、设备物理和计算机科学的基本概念。