Collaborative Research: SGER: Layout Generation Tools for Double-Gate-Transistor-Array-Based IC Designs

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Title: Collaborative Research: SGER: Layout Generation Tools for Double-Gate-Transistor-Array-Based IC DesignsCCF - 0904122 Maly, Wojciech (Carnegie-Mellon University)CCF - 0904124 Marek-Sadowska, Malgorzata (University of California-Santa Barbara)ABSTRACTThe proposed project aims to demonstrate the feasibility of an approach that can potentially remedy the huge productivity crisis plaguing the IC industry. The PIs propose a design methodology utilizing transistor-array-based canvases. The building block of a canvas is a vertical slit (VeS), dual-gate, junction-less transistor that can be fabricated with an SOI-like process. Canvases can be configured into useful circuits by customizing interconnects fabricated in a metallization process. In this way, one of the show stoppers of the modern design, lithographic imperfections, can be almost completely eliminated. The research proposed here is focused on developing basic layout tools for VeS-transistor arrays to show that dense transistor layouts are feasible, and to quantify the performance and power consumption of circuits built from VeS transistors.If successful, the methodology may have a huge effect on IC manufacturing and design practices.The design and manufacturing strategy proposed here has a very real chance of helping designersto make rapid use of the huge number of transistors available on a single chip without sacrificing performance and cost. The VeS transistor arrays can also serve as foundations for 3-D integration.