NSF Workshop; Electronic Design Automation -- Past, Present, and Future

点击翻译按钮获取中文摘要

CCF - 0930477 NSF Workshop; Electronic Design Automation -- Past, Present, and FutureCong, Jason University of California-Los Angeles ABSTRACTElectronic design automation (EDA) of very large-scale integrated (VLSI) circuits and systems is an important field in computer science and engineering. It has made a significant impact on the development of information technology?in particular in supporting the successful scaling of Moore?s Law over the past 40 years, which in turn has created the performance and cost-efficient information technology infrastructure that has transformed our lives and all of society. The success of the EDA is inspiring for many scientific and societal reasons.At the same time, the EDA field is facing serious challenges. For example, Non-Recurring Engineering (NRE) costs associated with VLSI circuit design are skyrocketing with estimates of over $30M per ASIC design undertaken. The rapid increase in the number of transistors available on a single chip leads to system-on-chip integration, with complex interactions between software and hardware, digital and analog, etc. Moreover, the field of applications enabled by semiconductor technology is growing at a rapid rate?ranging from very high performance microprocessors and signal processors to a broad array of low-power portable devices to micro sense/communicate/actuate networks of chips driven by very low per-unit cost and extremely low operating power. Designers must create chips that function properly in conventional digital and mixed-signal operation, as well as comprehend sensors that respond to signals from many physical domains such as pressure, temperature, chemical, and optical. The design problem is further compounded by the introduction of many new physical phenomena determining the performance of severely scaled semiconductor devices. For example, the power and performance characteristics of transistors are becoming statistical in nature. The probability of soft or permanent errors is much higher in the new generation of CMOS devices at 32nm or below or in new emerging non-CMOS devices. These present unprecedented challenges.In an earlier workshop jointly held in 2006 by the NSF and SRC a recommendation was made that research in design technology and tools be increased through a National Design Initiative. Such an effort was deemed to be critical ?to maintain U.S. leadership in design for integrated nano- and Microsystems.? The present workshop is to review the progress made under the National Design Initiative and evaluate whether new directions and topics should be added to the Initiative. The recommendations from this workshop will help to influence the design automation funding programs at the NSF.