CSR: Small: A Unified Many-Core Architecture for Enabling Speculative Multithreading and Transactional Memory

CSR：小型：用于启用推测多线程和事务内存的统一众核架构

• 批准号: 1017297
• 负责人: Hsien-Hsin Lee
• 金额: $ 35.18万
• 依托单位: Georgia Tech Research Corporation
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2010
• 资助国家: 美国
• 起止时间: 2010-08-01 至 2014-07-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=1017297&HistoricalAwards=false
• 关键词: CSR; Small; Unified; Many; Core

As multi-core and many-core processors are consensually becoming the de facto standard for all types of computing platforms, two techniques, Speculative Multithreading (SpecMT) and Transactional Memory (TM), have been intensively investigated on such platforms to enhance single-thread performance and to simplify the parallel programming model. These two computing models, proposed separately, share many common features in their underlying implementations. In this research, we give a holistic view and investigate a unified many-core architecture to support both technologies under one implementation. We first map SpecMT onto a hardware-based TM architecture and develop enabling techniques to showcase the performance potential while maintaining the benefit of a TM programming model. Each thread spawned speculatively or non-speculatively is transactified into a transaction. Compilers are used to determine when and where to initiate SpecMT with hardware to dynamically shepherd the decisions and throttle the extent of SpecMT. These transactions, executing different code regions, can be launched out of the sequential program order but must be committed in the original order with hardware support. This research focuses on (1) architectural support for enabling both SpecMT and TM, (2) compiler's support for SpecMT and thread transactification, (3) quantifying the benefits of different types of transactions, and (4) economical and feasible mechanisms to support SpecMT on heterogeneous many-core platforms such as the incoming integrated CPU-GPU systems. The success of such a unified many-core architecture will provide a foundation for delivering high performance for single-thread applications while improving the productivity for software developers substantially.

随着多核和多核处理器逐渐成为所有类型计算平台的事实标准，两种技术--推测多线程(Specmt)和事务存储器(TM)--在这些平台上得到了深入的研究，以提高单线程性能和简化并行编程模型。这两个单独提出的计算模型在其底层实现中有许多共同的特征。在这项研究中，我们给出了一个整体的观点，并研究了一个统一的多核架构，以在一个实现下支持这两种技术。我们首先将SpeMT映射到基于硬件的TM体系结构上，并开发使能技术来展示性能潜力，同时保持TM编程模型的优势。推测性地或非推测性地产生的每个线程被事务处理成一个事务。编译器用于确定何时何地启动SPECMT，并使用硬件动态监控决策并限制SPECMT的范围。这些执行不同代码区的事务可以不按顺序程序顺序启动，但必须在硬件支持下按原始顺序提交。这项研究的重点是：(1)支持SPECMT和TM的体系结构；(2)编译器对SPECMT和线程事务的支持；(3)量化不同类型事务的益处；(4)在即将到来的集成CPU-GPU系统等异类多核平台上支持SPECMT的经济可行的机制。这种统一的多核架构的成功将为单线程应用程序提供高性能的基础，同时显著提高软件开发人员的生产率。