CAREER: Compiler Techniques for Power-Efficient Protection Against Soft Errors

十年后，集成电路的特征尺寸预计将从现在的45 nm缩小到12 nm，软错误率将从每年一次增加到每天一次。国际半导体技术路线图（ITRS）报告将可靠性视为未来十年最重要的挑战之一，并指出软错误是主要威胁。软错误是暂时性故障，主要由宇宙辐射引起，可能导致错误的结果或整个系统故障。软错误对地面系统的影响既可怕又广泛，目标包括金融系统，医疗保健数据库，电网和通信基础设施。虽然已经做了很多工作，以保护计算系统的软错误，需要更多的功率，性能和面积有效的计划，以防止软错误是不可否认的。这项研究建立在现有的硬件和微架构的计划，以提供更省电的保护，从软错误，并将主要实现更好的应用程序分析。这项研究涉及开发应用程序分析，并转变应用程序使用微架构组件的方式，以最大限度地防止软错误。该项目的关键组成部分是：开发分析技术来模拟i）L1数据缓存，ii）寄存器文件和iii）流水线锁存器的漏洞，并使用漏洞估计来驱动编译器，微架构和混合技术，以提供组件的节能保护。iv）协同联合收割机组件级保护，以提供高能效的系统级保护。v）开发动态权衡功率和性能以获得可靠性的技术。vi）开发高能效多核保护方案。保持计算的可靠性，同时保持功率、性能和成本效益，对于保持技术进步的步伐、确保国家利益以及最终提高生活质量至关重要。PI计划公开发布RP2Explore：一个编译器微架构工具包，用于定量研究基于GCC的可编程平台中的功耗，性能，面积，可靠性和热权衡，以实现轻松的适应性和最大的影响。

In a decade feature sizes of integrated circuits are expected to shrink from present day 45nm to 12nm, increasing soft error rates from once-per-year to once-per-day. The International Technology Roadmap for Semiconductors (ITRS) report recognizes reliability as one of the most important challenges for the next decade, and points out that soft errors are the primary threat. Soft errors are transient faults, caused mostly by cosmic radiations and can lead to incorrect results or total system failure. The impact of soft errors on terrestrial systems can be both dire and sweeping, with targets including financial systems, health-care databases, power-grid, and communication infrastructure. Although much work has been done towards protecting computing systems from soft errors, the need for even more power, performance and area-efficient schemes for protection against soft errors is undeniable.This research builds upon existing hardware and microarchitectural schemes to provide even more power-efficient protection from soft errors, and will primarily be achieved by better application analysis. This research involves developing application analysis, and transforming the way application uses microarchitectural components to maximize protection from soft errors. Key components of this project are to: Develop analytical techniques to model vulnerability of i) L1 data cache, ii) register file, and iii) pipeline latches, and use the vulnerability estimates to drive compiler, microarchitectural, and hybrid techniques to provide power-efficient protection of the components. iv) Synergistically combine component-level protection to provide power-efficient, system-level protection. v) Develop techniques for dynamically trading off power and performance for reliability. vi) Develop schemes for power-efficient multi-core protection. Keeping computation reliable, and yet power, performance and cost efficient is crucial inmaintaining the pace of technological advancement, securing national interests, and ultimately in improving the quality of life. PI plans to make public release of RP2Explore: a compiler-microarchitecture toolkit for quantitative study of power, performance, area, reliability, and thermal trade-offs in programmable platforms based on GCC for easy adaptability and maximal impact.