CSR: Small: Scaling the Real-time Capabilities of Powertrain Controller in Automotive Systems

CSR：小：扩展汽车系统中动力总成控制器的实时功能

• 批准号: 1525855
• 负责人: Aviral Shrivastava
• 金额: $ 44.95万
• 依托单位: Arizona State University
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2015
• 资助国家: 美国
• 起止时间: 2015-10-01 至 2020-09-30
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=1525855&HistoricalAwards=false
• 关键词: CSR; Small; Scaling; Real; time

CSR: Small: Scaling the Real-time Capabilities of Powertrain Controllers in Automotive SystemsScratchPad Memory(SPM)-based many-core architecture is a promising concept to improve the real-time capability of computing systems required in safety-critical applications. Demonstrating the proposed approach for powertrain controllers is just the first step and has the potential to enable the rapidly increasing fields of internet-of-things (IoT), avionics, robotics, cyber-infrastructure, and much more. An open-source cycle-accurate simulator of the SPM-based many-core processor, and a low level virtual machine (llvm) compiler will be developed as the outcome of this research significantly advancing this technology. This project will develop architecture, compilation, scheduling techniques, and real- time analysis to scale up the real-time capabilities of powertrain controllers of automotive systems. Powertrain controller is a safety-critical, hard-real-time controller in modern automobiles, directly responsible for the operation of the engine and transmission. The complexity of powertrain control applications is rapidly increasing in a quest to fulfill increasingly stringent regulations on the fuel- efficiency and emissions. To meet this demand, the real-time capability of powertrain engine control units (ECU) must also improve. Real-time capability of a processor is essentially a measure of how many/complex/frequent tasks can be guaranteed to finish in given deadlines. The challenge is that the real-time capability of a processor cannot be improved by traditional performance enhancing techniques, e.g., increasing frequency, adding more on-chip memory, or by adding caches. This research will employ (SPMs) instead of caches to improve the real-time capability of powertrain ECUs. SPM partitioning, mapping/scheduling, SPM management techniques and real-time analyses for SPM-based many-core architecture (in which each core has an SPM instead of a cache) will be developed. This will be done for two data management schemes: one for task-level management, where all the code and data of the task are brought into the SPM at the beginning of the task and the other for function-level management, which enables executing applications on processors with much smaller SPM sizes, and can still be efficient through various compiler optimizations.

CSR：小：扩展汽车系统中动力总成控制器的实时能力基于scratchpad Memory（SPM）的多核架构是一个很有前途的概念，可以提高安全关键应用中计算系统的实时能力。演示动力总成控制器的拟议方法只是第一步，并且有可能使快速增长的物联网（IoT），航空电子，机器人，网络基础设施等领域成为可能。基于spm的多核处理器的开源周期精确模拟器和低级虚拟机（llvm）编译器将作为本研究的成果，显著推进该技术的发展。该项目将开发架构、编译、调度技术和实时分析，以扩大汽车系统动力总成控制器的实时能力。动力总成控制器是现代汽车中对安全至关重要的硬实时控制器，直接负责发动机和变速器的运行。为了满足日益严格的燃油效率和排放法规，动力系统控制应用的复杂性正在迅速增加。为了满足这一需求，动力总成发动机控制单元（ECU）的实时性能也必须得到提高。处理器的实时能力本质上是衡量在给定期限内可以保证完成多少/复杂/频繁的任务。挑战在于处理器的实时能力不能通过传统的性能增强技术来提高，例如，增加频率，增加更多的片上内存，或者增加缓存。本研究将采用SPMs代替缓存来提高动力总成ecu的实时性能。将开发SPM分区、映射/调度、SPM管理技术和基于SPM的多核体系结构（每个核有一个SPM而不是一个缓存）的实时分析。这将用于两种数据管理方案：一种用于任务级管理，其中任务的所有代码和数据在任务开始时被引入SPM；另一种用于功能级管理，它允许在SPM大小小得多的处理器上执行应用程序，并且通过各种编译器优化仍然可以高效地执行。

项目成果

Efficient Heap Data Management on Software Managed Manycore Architectures

• DOI: 10.1109/vlsid.2019.00065
• 发表时间: 2019-01
• 期刊: 2019 32nd International Conference on VLSI Design and 2019 18th International Conference on Embedded Systems (VLSID)
• 作者: Jinn Lin;Jing Lu;Jian Cai;Aviral Shrivastava