CSR: Small: Scaling the Real-time Capabilities of Powertrain Controller in Automotive Systems

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CSR: Small: Scaling the Real-time Capabilities of Powertrain Controllers in Automotive SystemsScratchPad Memory(SPM)-based many-core architecture is a promising concept to improve the real-time capability of computing systems required in safety-critical applications. Demonstrating the proposed approach for powertrain controllers is just the first step and has the potential to enable the rapidly increasing fields of internet-of-things (IoT), avionics, robotics, cyber-infrastructure, and much more. An open-source cycle-accurate simulator of the SPM-based many-core processor, and a low level virtual machine (llvm) compiler will be developed as the outcome of this research significantly advancing this technology. This project will develop architecture, compilation, scheduling techniques, and real- time analysis to scale up the real-time capabilities of powertrain controllers of automotive systems. Powertrain controller is a safety-critical, hard-real-time controller in modern automobiles, directly responsible for the operation of the engine and transmission. The complexity of powertrain control applications is rapidly increasing in a quest to fulfill increasingly stringent regulations on the fuel- efficiency and emissions. To meet this demand, the real-time capability of powertrain engine control units (ECU) must also improve. Real-time capability of a processor is essentially a measure of how many/complex/frequent tasks can be guaranteed to finish in given deadlines. The challenge is that the real-time capability of a processor cannot be improved by traditional performance enhancing techniques, e.g., increasing frequency, adding more on-chip memory, or by adding caches. This research will employ (SPMs) instead of caches to improve the real-time capability of powertrain ECUs. SPM partitioning, mapping/scheduling, SPM management techniques and real-time analyses for SPM-based many-core architecture (in which each core has an SPM instead of a cache) will be developed. This will be done for two data management schemes: one for task-level management, where all the code and data of the task are brought into the SPM at the beginning of the task and the other for function-level management, which enables executing applications on processors with much smaller SPM sizes, and can still be efficient through various compiler optimizations.