SHF: Small: Design/Automation for Synthesizable and Scaling Friendly Analog/Mixed-Signal Circuits

SHF：小型：可综合且可扩展的模拟/混合信号电路的设计/自动化

• 批准号: 1527320
• 负责人: Nan Sun
• 金额: $ 45万
• 依托单位: University of Texas at Austin
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2015
• 资助国家: 美国
• 起止时间: 2015-06-15 至 2018-05-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=1527320&HistoricalAwards=false
• 关键词: SHF; Small; Design; Automation; Synthesizable

The goal of the proposed research is to tackle two critical challenges for conventional analog and mixed-signal circuits to address scaling incompatibility and low design productivity. The proposed time-domain analog mixed signal circuits are scaling compatible, and can achieve higher performance with substantially reduced chip area, power, and cost. They address the critical real-world challenge of cost effectively integrating analog-mixed-signal circuits with digital functions. They can enable emerging applications that demand ultra-low-power and ultra-low voltage solutions. The proposed research design for synthesizability and new synthesis tools also has significant impacts on enhancing design productivity, leading to reduced cost, enhanced capability, shortened time-to-market, and improved reliability. The proposed novel time domain analog-mixed-signal circuits process analog information in the time or phase domain. Thus, they naturally benefit from CMOS scaling with increased transistor speed and reduced delay. Moreover, this proposal opens up a new research direction of analog-mixed-signal design for synthesizability, the objective of which is to alleviate the difficulty in analog synthesis by intentionally creating new topologies that are synthesis friendly. New analog synthesis tools will be developed, with focus on developing compact and high-fidelity models to reduce runtime and tackle process variation. Several previously untouched issues will be addressed, such as sensitive node protection, current flow constraints, and substrate noise coupling. A new machine-learning based framework will also be developed to further increase automation level.

拟议研究的目标是解决传统模拟和混合信号电路的两个关键挑战，以解决缩放不兼容性和低设计生产率。所提出的时域模拟混合信号电路是缩放兼容的，并且可以以大幅降低的芯片面积、功耗和成本来实现更高的性能。它们解决了将模拟混合信号电路与数字功能经济有效地集成的关键现实挑战。它们可以支持需要超低功耗和超低电压解决方案的新兴应用。所提出的可综合性研究设计和新的综合工具也对提高设计生产率产生了重大影响，从而降低了成本，增强了能力，缩短了上市时间，提高了可靠性。所提出的新颖时域模拟混合信号电路在时域或相域中处理模拟信息。因此，它们自然受益于CMOS缩放，提高了晶体管速度并降低了延迟。此外，这一建议开辟了一个新的研究方向的模拟混合信号设计的可合成性，其目标是减轻模拟合成的困难，有意创造新的拓扑结构，是合成友好。将开发新的模拟合成工具，重点是开发紧凑和高保真的模型，以减少运行时间和处理过程变化。几个以前未触及的问题将得到解决，如敏感节点保护，电流限制，和基板噪声耦合。我们亦将开发一个新的机器学习框架，以进一步提高自动化水平。