SHF: Small: Design/Automation for Synthesizable and Scaling Friendly Analog/Mixed-Signal Circuits

拟议研究的目标是解决传统模拟和混合信号电路的两个关键挑战，以解决比例不兼容和设计生产率低的问题。所提出的时域模拟混合信号电路是可缩放兼容的，并且可以在大幅降低芯片面积、功耗和成本的情况下获得更高的性能。它们解决了经济高效地将模拟-混合信号电路与数字功能集成在一起的关键现实挑战。它们可以支持需要超低功耗和超低电压解决方案的新兴应用。拟议的可合成性研究设计和新的综合工具也对提高设计生产率产生了重大影响，从而降低了成本，增强了能力，缩短了上市时间，并提高了可靠性。提出的新型时域模拟-混合信号电路在时间域或相域处理模拟信息。因此，它们自然受益于具有更高晶体管速度和更少延迟的CMOS扩展。此外，该方案还开辟了模拟-混合信号可综合性设计的新的研究方向，其目的是通过有意地创造出对综合友好的新的拓扑结构来减轻模拟综合的难度。将开发新的模拟合成工具，重点是开发紧凑和高保真的模型，以减少运行时间和处理工艺变化。将解决几个以前未触及的问题，如敏感节点保护、电流限制和衬底噪声耦合。还将开发一个新的基于机器学习的框架，以进一步提高自动化水平。

The goal of the proposed research is to tackle two critical challenges for conventional analog and mixed-signal circuits to address scaling incompatibility and low design productivity. The proposed time-domain analog mixed signal circuits are scaling compatible, and can achieve higher performance with substantially reduced chip area, power, and cost. They address the critical real-world challenge of cost effectively integrating analog-mixed-signal circuits with digital functions. They can enable emerging applications that demand ultra-low-power and ultra-low voltage solutions. The proposed research design for synthesizability and new synthesis tools also has significant impacts on enhancing design productivity, leading to reduced cost, enhanced capability, shortened time-to-market, and improved reliability. The proposed novel time domain analog-mixed-signal circuits process analog information in the time or phase domain. Thus, they naturally benefit from CMOS scaling with increased transistor speed and reduced delay. Moreover, this proposal opens up a new research direction of analog-mixed-signal design for synthesizability, the objective of which is to alleviate the difficulty in analog synthesis by intentionally creating new topologies that are synthesis friendly. New analog synthesis tools will be developed, with focus on developing compact and high-fidelity models to reduce runtime and tackle process variation. Several previously untouched issues will be addressed, such as sensitive node protection, current flow constraints, and substrate noise coupling. A new machine-learning based framework will also be developed to further increase automation level.