Collaborative Research: Surface Engineering and Atomic Layer Deposition of Dielectrics on Two-Dimensional Atomic Crystals for Device Application

这笔赠款由电子、通信和网络系统(ECCS)部门的电子、光子学和磁性设备(EPMD)计划和材料研究(DMR)部门的电子和光子材料(EPM)计划联合资助。微型化是半导体行业技术进步的核心。然而，随着当前的结构和材料达到物理定律施加的限制，需要对基本构建块--金属氧化物半导体场效应晶体管(MOSFET)--的设计进行实质性的改变。这个难题的一个解决方案是使用新材料，例如我们最近才开始详细研究的二维(2D)原子晶体。这种材料是制造高质量器件的终极小型介质。这项工作的目标是开发和加深我们对这些纳米结构材料的性质的理解，并介绍具有不同于传统技术的工作原理的器件结构，同时继续受益于已经存在的硅技术的丰富经验。这项工作回应了人们普遍认识到的在纳米电子学和技术方面取得进展的需要，因为目前的范例正在达到基本的物理和经济极限。这项工作的成果还包括新的纳米制造技术和纳米电子计量学，这将增加国家纳米技术组合，这是美国未来技术主导地位的重要组成部分。没有高素质的科学家和工程师，技术就不能先进或应用。两名研究生，一名来自密歇根州立大学和一名乔治梅森大学，将获得博士学位，同时与彼此和我们在NIST的合作者进行非常密切的互动，为他们在工业、学术界和政府的职业生涯做好准备。许多本科生也将受益，例如通过做他们的高级设计项目。部分研究将纳入目前由私人投资主任教授的研究生水平课程，结果将在研讨会、会议和同行评议的出版物上公布。这项提议的目的是在表面制备方法领域产生新的知识，以便能够在二维(2D)原子晶体MOSFET应用上原子层沉积高质量的电介质。这种2D材料，例如MoS2和WSe2的孤立单层和几层，将在晶片规模上生长，用于原位表征和电路集成。它们的表面将被精心设计成自组装的分子单层，以便在电介质的原子层沉积过程中形成高质量的界面。在电介质沉积过程中，对表面制备结果进行现场分析，并与物理吸附电介质进行比较。这种表面改性将使高性能2D原子晶体MOSFET和电路仍然与硅技术兼容。这些新器件的特点将是更好的栅极控制、更快的操作和更低的泄漏功耗，同时减少面积和成本。获得的表面制备技术将使2D MOSFET和电子电路能够集成，并作为展示材料和界面属性的平台。这项工作将利用2D纳米材料和器件的固有优势，并有可能对下一代器件和电子电路产生变革影响。

This grant is funded jointly by the Electronics, Photonics, and Magnetic Devices (EPMD) Program in the Division of Electrical, Communications and Cyber Systems (ECCS) and by the Electronic and Photonic Materials (EPM) Program in the Division of Materials Research (DMR).Miniaturization lies in the heart of technological advancement in the semiconductor industry. However, a substantial change in the design of the basic building block which is the metal oxide semiconductor field effect transistor (MOSFET) is required as the current architecture and materials are reaching limits imposed by the laws of physics. A solution to this conundrum is the use of new materials such as two dimensional (2D) atomic crystals that we have only recently begun to investigate in detail. Such materials are the ultimate small medium allowing the fabrication of high quality devices. The goal of this work is to exploit and further our understanding of the properties of these nanostructured materials and to introduce device structures with operational principles different than the conventional technology, while at the same time continuing to benefit from the already existing vast experience with silicon technology. This work responds to the widely recognized need for progress in nanoelectronics and technology as the current paradigm is reaching the fundamental physical and economic limit. The outcomes of this work also include new nano-fabrication technology and nanoelectronic metrology which will add to the national nanotechnology portfolio, a vital component for the future technological dominance of the USA. Technologies cannot be advanced or applied in the absence of highly qualified scientists and engineers. Two graduate students, one from UMBC and one George Mason University will gain their Ph.D. while interacting very closely with each other and our collaborators at NIST, preparing them for careers in industry, academia and government. Many undergraduate students will also be benefit, for example by doing their senior design projects. Parts of the research will be integrated into graduate level courses currently taught by both PIs and results will be presented in seminars, conferences and peer reviewed publications. The goal of this proposal is to produce new knowledge in the area of surface preparation methods so as to enable atomic layer deposition of high-quality dielectrics on two-dimensional (2D) atomic crystals MOSFET applications. The 2D materials, such as the isolated monolayer and few-layers of MoS2 and WSe2 will be grown at wafer scale for both in-situ characterization and circuit integration. Their surface will be carefully engineered with self-assembled monolayers of molecules to enable the formation of high-quality interface during the atomic layer deposition of dielectrics. The surface preparation results will be analyzed in-situ during the deposition of dielectrics, and compared with physisorbed dielectrics. This surface modification will enable high-performance 2D atomic crystal MOSFETs and circuits which will nevertheless remain compatible with silicon technology. These new devices will be characterized by better gate control, faster operation and lower leakage power dissipation at reduced area and cost. The acquired surface preparation technology will enable integration of 2D MOSFETs and electronic circuits, and act as platforms to demonstrate the properties of materials and interfaces. This work will exploit the inherent advantages of the 2D nanomaterials and devices, with the potential to have transformational impact on the next generation of devices and electronic circuits.