Polymer-wrapped Carbon Nanotubes for high performance field effect transistors

该项目的目的是通过自组装半导体碳纳米管来制造高性能的场效应晶体管。虽然对更大的信息存储容量和更高的信息处理速度的需求比以往任何时候都更大，但传统硅基材料的向下可伸缩性正接近其极限，推动着对新技术的探索。单壁碳纳米管(SWNTs)作为一种坚固耐用的纳米材料，具有独特的电学性质，具有前所未有的小型化潜力。由于它们的半导体特性和弹道(无散射)传输，它们满足了对具有低成本技术潜力的高性能半导体的需求。尽管碳纳米管器件的载流子迁移率比实际的(硅基)晶体管高出1000倍，但它们在工业应用中的应用仍然难以捉摸。最严重的问题是：i)无法生产大量具有相同物理性质的纳米管(半导体)，ii)难以将单个纳米管放置在表面的预定位置。这个项目将通过利用共轭聚合物包裹的单壁碳纳米管来获得i)富含半导体单壁碳纳米管的样品和ii)通过自组装控制放置来解决这两个问题。半导体管的识别将通过用特定的共轭聚合物包裹它们来实现。此外，聚合物将被用作锚定系统，以定位特定衬底位置上的单壁碳纳米管，并通过自组装制造晶体管。

The aim of this project is to fabricate highly performing field effect transistors by self-assembling semiconducting carbon nanotubes. While the demand for larger information storage capacity and higher speed information processing are greater than ever, the down scalability of conventional silicon-based materials are approaching their limits, driving the search for new technologies. Single wall carbon nanotubes (SWNTs) offer unprecedented potential for miniaturization as a robust, nanometer size material with unique electronic properties. Due to their semiconducting properties and ballistic (scattering free) transport, they address the need for highly performing semiconductors which have the potential of a low cost technology. In spite of the fact that carbon nanotube devices shown carrier mobilities of up to 1000 times higher than that of the actual (Si based) transistors, their use in industrial application remains elusive. The most serious problems are: i) the inability to produce large quantities of nanotubes with the same physical properties (semiconducting), ii) the difficulty to place individual nanotubes in predetermined positions on a surface. This project will address both problems by taking advantage of conjugated polymer wrapped SWNTs to obtain i) samples enriched of semiconducting SWNTs and ii) controlled placement through self-assembly. Recognition of semiconducting tubes will be achieved by wrapping them with specific conjugated polymers. Furthermore, the polymers will be used as anchoring system to address the SWNTs on specific substrates positions and fabricate transistors by self-assembly.