I/UCRC FRP: Collaborative Research: Testability and timing analysis in nanoscale designs in the presence of process variations

I/UCRC FRP：协作研究：存在工艺变化的纳米级设计中的可测试性和时序分析

• 批准号: 1432348
• 负责人: Sarma Vrudhula
• 金额: $ 10万
• 依托单位: Arizona State University
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2014
• 资助国家: 美国
• 起止时间: 2014-09-15 至 2016-08-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=1432348&HistoricalAwards=false
• 关键词: UCRC; FRP; Collaborative; Research; Testability

A significant challenge for embedded systems is developing the high-performance, reliable, low cost, and low-power integrated circuits. This project addresses this challenge by developing accurate testability and timing analysis techniques for integrated circuits. The main objective of this effort is to address timing-related reliability, testing and design challenges faced by the semiconductor industry due to significant increase in process variations. The project will develop new methods for modeling the process variability that benefit from advanced data structures and novel algorithms. A new direction in determining gate delay models in the presence of process variations is investigated. The goal is to reduce modeling errors and is expected to identify critical path delay faults that current methods skip. Moreover, it is expected to result in more accurate estimates for the delay of the circuit.The proposed research activities will help semiconductor companies in developing reliable and faster integrated circuits and microprocessors. This will have impact on the society since cell-phones, cars, airplanes, unmanned vehicles, and biomedical devices are a major factor in the quality of human life. The fundamental modeling of process variations will be developed with the center member companies, ensuring rapid technology transfer and uptake of new methods. The work is supported by the Industry Advisory Board as well as individual industry members of the center and has the potential to extend the center research portfolio while potentially attracting new members. The proposed research will be used as a vehicle to help students develop interests and abilities to conduct research in the VLSI design and test automation area, and undergraduates will be inspired for graduate studies.

高性能、可靠、低成本、低功耗的集成电路是嵌入式系统面临的一个重大挑战。该项目通过开发集成电路的精确可测性和时序分析技术来解决这一挑战。这项工作的主要目标是解决半导体行业由于工艺变化显著增加而面临的与时序相关的可靠性、测试和设计挑战。该项目将开发新的方法来模拟过程的变化，受益于先进的数据结构和新颖的算法。一个新的方向，在确定门延迟模型中存在的工艺变化进行了研究。其目标是减少建模误差，并预计将确定当前方法跳过的关键路径延迟故障。此外，预计这将导致更准确的估计电路的延迟。拟议的研究活动将有助于半导体公司开发可靠和更快的集成电路和微处理器。这将对社会产生影响，因为手机、汽车、飞机、无人驾驶车辆和生物医学设备是人类生活质量的主要因素。将与中心成员公司一起开发过程变化的基本建模，确保快速技术转移和新方法的采用。这项工作得到了行业咨询委员会以及该中心的个别行业成员的支持，并有可能扩大该中心的研究组合，同时可能吸引新成员。拟议的研究将被用来作为一种工具，以帮助学生发展的兴趣和能力，在超大规模集成电路设计和测试自动化领域进行研究，本科生将受到启发，研究生学习。