IRES: International Research Experience for Students on Design Automation of Three-Dimensional Integrated Circuits
IRES: International Research Experience for Students on Design Automation of Three-Dimensional Integrated Circuits
批准号:
1456867
负责人:
Yiyu Shi
金额:
$24.97万
依托单位国家:
美国
项目类别:
Standard Grant
财政年份:
2015
资助国家:
美国
项目状态:
已结题
起止时间:
2015-11-01 至 2015-10-31
中文摘要
点击翻译按钮获取中文摘要
英文摘要
Non-Technical Abstract: This project will enable U.S. students to conduct high-quality research on design automation of three dimensional integrated circuits (3D ICs), in collaboration with their faculty mentors at National Tsing Hua University (NTHU) in Taiwan. Such experiences expose U.S. students to the international research community at a critical early stage in their careers. It is expected that through participating in this project, U.S. students will gain extensive experience on the research of 3D ICs, on the international semiconductor prospects, on the culture in Taiwan, and on performing and collaborating in an international environment in general. The experience will also be shared to the broader community through the involvement of personal social media, Web 2.0 based forum, carefully integrated activities such as research for undergraduate students, as well as outreach events for local schools. In particular, this project will have a dedicated focus on the career development of minorities and underrepresented groups.Technical Abstract: This IRES project provides U.S. students with valuable research experience related to the design automation of three-dimensional integrated circuits (3D ICs) in Hsin-Chu, Taiwan, where the world's largest semiconductor industry is located. The project will select five (5) graduate students and two (2) undergraduate students nation-wide each year and support them to visit the Computer Science Department at National Tsing Hua University (NTHU) over a period of twelve (12) weeks. They will be mentored by the professors at NTHU. The primary research objective is to address fundamental issues in 3D ICs and to bridge the gap between advanced 3D fabrication processes and the designers using these technologies. The Moore's Law states that the transistor density on integrated circuits doubles approximately every two years. However, this trend is becoming increasingly difficult to keep due to the high cost associated with semiconductor scaling. Accordingly, the semiconductor industry has started to look for alternative technologies that offer a path beyond the limits of device scaling. Among all the possible alternatives, the three-dimensional integrated circuit (3D IC) is generally considered to be the most promising one, at least in the next decade, for its full compatibility with current technologies. Instead of making transistors smaller, it stacks multiple chips vertically for higher integration density, shorter wirelength, smaller footprint, higher speed, and lower power consumption. As such, 3D IC has become a very hot topic in academic research and industry practice in recent years. The students will work on projects related to the yield enhancement of 3D ICs and the novel design flows for two promising 3D technologies - interposer-based 3D ICs and monolithic 3D ICs. The research can significantly increase the yield of 3D ICs without involving area penalty. It is anticipated that the breakthroughs from this IRES project at NTHU can have a direct impact on the 3D IC industry.
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