Design and Characterisation of Basic Components for 160 Gbit/s Data Rate in 0.13 µm SiGe:C Hetero Bipolar Technology

采用 0.13 µm SiGe:C 异质双极技术实现 160 Gbit/s 数据速率的基本组件的设计和表征

• 批准号: 219211669
• 负责人: Professor Dr.-Ing. Andreas Thiede
• 金额: --
• 依托单位: Fachgebiet Höchstfrequenzelektronik (HFE)
• 依托单位国家: 德国
• 项目类别: Research Grants
• 财政年份: 2012
• 资助国家: 德国
• 起止时间: 2011-12-31 至 2016-12-31
• 项目状态: 已结题
• 来源: https://gepris.dfg.de/gepris/projekt/219211669?language=en
• 关键词: Design; Characterisation; Basic; Components; 160

Subject of the proposed project is the development of key components, which enable data rates up to 160 Gbit/s by electronic means for the first time. The project is based on the SG13G2 technology of IHP, which was released for academic access recently. In close context with integrated circuit design, test methods are to be devised, because appropriate commercial measurement equipment is not available.In the first project phase, a PLL, and as its essential parts a VCO and frequencydivider, are to be developed.On this basis, a multiplexer for the generation of 160 Gbit/s data streams istargeted in the final project year.

该项目的主题是开发关键组件，首次通过电子手段实现高达160 Gbit/s的数据速率。该项目基于IHP的SG13G2技术，该技术最近向学术界开放。在集成电路设计的密切背景下，由于没有适当的商用测量设备，必须设计测试方法。在第一个项目阶段，将开发一个锁相环，以及作为其基本部件的压控振荡器和分频器。在此基础上，多路复用器的目标为产生160 Gbit/s的数据流，最终在项目年完成。

项目成果

An integrated 118.4 to122 GHz low noise phase-locked loop (PLL) in 0.13 µm SiGe BiCMOS technology

采用 0 13 µm SiGe BiCMOS 技术的集成 118 4 至 122 GHz 低噪声锁相环 (PLL)

• DOI: 10.1109/gemic.2016.7461611
• 发表时间: 2016
• 期刊: 2016 German Microwave Conference (GeMiC)
• 作者: U. Ali;M. Bober;A. Thiede
• 通讯作者: A. Thiede

Design of voltage controlled oscillators (VCOs) in D-band and their phase noise measurements using frequency down-conversion

D 频段压控振荡器 (VCO) 的设计及其使用下变频的相位噪声测量

• DOI: 10.1109/eumic.2016.7777554
• 发表时间: 2016
• 期刊: 2016 11th European Microwave Integrated Circuits Conference (EuMIC)
• 作者: U. Ali;M. Bober;A. Thiede
• 通讯作者: A. Thiede