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I-Corps: Sygnal: Compact, Low Power, High Performance Digital Circuits using Threshold Logic

I-Corps: Sygnal: Compact, Low Power, High Performance Digital Circuits using Threshold Logic
I-Corps:Sygnal:使用阈值逻辑的紧凑、低功耗、高性能数字电路
批准号:
1565921
负责人:
Sarma Vrudhula
金额:
$5.0万
依托单位:
依托单位国家:
美国
项目类别:
Standard Grant
财政年份:
2015
资助国家:
美国
项目状态:
已结题
起止时间:
2015-11-01 至 2016-12-31

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中文摘要
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英文摘要
Digital circuits made up of transistors are the components inside computer chips that operate nearly all the computing devices (e.g. servers, desktops, laptops, tablets, smartphones, and wearables) in use today. Although we can pack more than a billion transistors in one square centimeter, it is becoming increasingly difficult to make full use of them because they consume too much energy. Today, methods to lower the energy consumption always come with a price?reduced speed, which in turn makes them less capable to perform more challenging tasks (e.g. face recognition by smartphone). This team has developed a new way to design digital circuits that consume much less energy (ranging from 20% to 40%) without sacrificing performance and can be made smaller. Thus the proposed technology will reduce energy consumption of digital systems, extend the battery life and/or improve the capabilities of laptops, tablets, smartphones and other battery powered systems. Another significant advantage of the proposed circuits is that they can be designed with the same commercial tools and the same semiconductor fabrication processes that are used by companies today, enabling easy and rapid adoption by industry. High performance, low-­‐power digital circuits are required for a large class of products including smartphones and wearables. Current semiconductor solutions rely on clock and power management to reduce energy consumption, but reduction in energy per operation has relied on technology scaling with diminishing returns. This I-Corps team has developed a digital circuit implementation technology, that reduces joules/operation and area without compromising speed, and is based on three fundamental advances in CMOS logic design, all patent protected. (1) Robust, low power threshold logic circuit design, (TLG), that combines the functionality of a large set of complex functions, and a flip-­‐flop into a single cell. (2) A standard cell library of TLGs, which is perfectly compatible with conventional cell libraries used by commercial synthesis, optimization and physical design tools. (3) Software that optimizes a given logic network using cells and conventional logic cells, resulting in a hybrid design. All three - the circuit architecture, cell library and design software - were designed to ensure 100% compatibility with existing commercial design flows, allowing fully automated synthesis, optimization and layout using commercial tools.
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