RIA: Stochastic Models in Partitioning for Testability of Digital Circuits

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This research is on developing models for evaluating hierarchal testability of circuits. Three topics are being pursued. First, stochastic models for circuit structure, used for obtaining analytical expressions of controllability and observability, are being explored. New testability metrics and fast testability evaluation of IC's based on the stochastic models are being investigated. Second, a unified framework for expressing hierarchal testability metrics is being established. This allows representation of any testability metric for the purpose of hierarchal testability analysis. Formal methods of composing testability metrics are being developed. Third, efficient algorithms for doing the partitioning for testability are being designed and evaluated. Central to the approach is the development of a discrete hazard function that quantifies for each level in a circuit the difficulty to fault propagation exhibited by the circuit structure.