RIA: Stochastic Models in Partitioning for Testability of Digital Circuits

本研究旨在建立评估电路层次化测试性的模型。目前正在研究三个主题。首先，正在探索电路结构的随机模型，用于获得可控性和能观性的解析表达式。基于随机模型的集成电路新的可测试性度量和快速可测试性评估正在研究之中。其次，正在建立表达层次化可测试性度量的统一框架。这允许表示用于分层可测试性分析的任何可测试性度量。组成可测试性度量的正式方法正在开发中。第三，正在设计和评估用于进行可测试性划分的高效算法。该方法的中心是开发离散危险函数，该函数为电路中的每一级量化电路结构所表现出的故障传播的难度。

This research is on developing models for evaluating hierarchal testability of circuits. Three topics are being pursued. First, stochastic models for circuit structure, used for obtaining analytical expressions of controllability and observability, are being explored. New testability metrics and fast testability evaluation of IC's based on the stochastic models are being investigated. Second, a unified framework for expressing hierarchal testability metrics is being established. This allows representation of any testability metric for the purpose of hierarchal testability analysis. Formal methods of composing testability metrics are being developed. Third, efficient algorithms for doing the partitioning for testability are being designed and evaluated. Central to the approach is the development of a discrete hazard function that quantifies for each level in a circuit the difficulty to fault propagation exhibited by the circuit structure.