An Undergraduate Digital Systems Laboratory With Emphasis OnVLSI
以超大规模集成电路为重点的本科数字系统实验室
基本信息
- 批准号:9351291
- 负责人:
- 金额:$ 4.47万
- 依托单位:
- 依托单位国家:美国
- 项目类别:Standard Grant
- 财政年份:1993
- 资助国家:美国
- 起止时间:1993-09-01 至 1996-02-29
- 项目状态:已结题
- 来源:
- 关键词:
项目摘要
9351291 Vrudhula The aim of this project is to establish an undergraduate digital systems design laboratory with emphasis on VLSI. This laboratory is part of a new two- course sequence offered to seniors in computer engineering. The primary objectives of this project are: (1) to expose the students to all aspects of systems design, starting from the behavioral level down to the layout level; and (2) to teach the fundamental engineering discipline involved in evaluation, testing and redesign. These primary objectives are being achieved by addressing the following important aspects of systems design: (1) use of multiple levels of abstraction; (2) methods of evaluating a design in terms of performance, area, design time and cost at each level; (3) examining tradeoffs among the possible choices that are available at each level; (4) understanding the limits of fabrication technology, causes and effects of failures and fault models; and (5) understanding that design and test cannot be separate activities by introducing design for testability. The purpose of the laboratory is to provide hands on experience through the use of the latest CAD tools and a computing environment that reflects the state-of-the-art in industry. The tools eliminate much of the mundane aspects of the design and allow the students to focus on the important high level design issues. Theoretical knowledge and practical design experience are carefully balanced through a set of realistic design projects that involve the students in all aspects of systems design. In addition, the laboratory provides for rapid prototyping of the designs through the use of Field Programmable Gate Arrays. This allows students to build, exercise, and re-evaluate designs. ***
9351291 Vrudhula这个项目的目标是建立一个本科数字系统设计实验室,重点是超大规模集成电路。这个实验室是为计算机工程专业的大四学生开设的新的两门课程的一部分。这个项目的主要目标是:(1)让学生接触到系统设计的各个方面,从行为层面到布局层面;以及(2)教授涉及评估、测试和重新设计的基本工程学科。这些主要目标是通过解决系统设计的下列重要方面来实现的:(1)使用多个抽象级别;(2)根据每个级别的性能、面积、设计时间和成本来评估设计的方法;(3)检查在每个级别可用的可能选择之间的权衡;(4)了解制造技术的限制、故障和故障模型的原因和影响;以及(5)通过引入可测试性设计来理解设计和测试不能是分开的活动。该实验室的目的是通过使用最新的CAD工具和反映工业最先进水平的计算环境来提供实践经验。这些工具消除了设计的大部分平凡方面,使学生能够专注于重要的高级设计问题。理论知识和实际设计经验通过一套让学生参与系统设计各个方面的现实设计项目得到仔细的平衡。此外,该实验室通过使用现场可编程门阵列对设计进行快速原型制作。这使学生能够构建、练习和重新评估设计。***
项目成果
期刊论文数量(0)
专著数量(0)
科研奖励数量(0)
会议论文数量(0)
专利数量(0)
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Sarma Vrudhula其他文献
Thermal aware floorplanning incorporating temperature dependent wire delay estimation
- DOI:
10.1016/j.micpro.2015.09.013 - 发表时间:
2015-11-01 - 期刊:
- 影响因子:
- 作者:
Andreas Thor Winther;Wei Liu;Alberto Nannarelli;Sarma Vrudhula - 通讯作者:
Sarma Vrudhula
Sarma Vrudhula的其他文献
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{{ truncateString('Sarma Vrudhula', 18)}}的其他基金
IUCRC Phase I Arizona State University: Center for Intelligent, Distributed, Embedded, Applications and Systems (IDEAS)
IUCRC 第一阶段亚利桑那州立大学:智能、分布式、嵌入式、应用和系统中心 (IDEAS)
- 批准号:
2231620 - 财政年份:2023
- 资助金额:
$ 4.47万 - 项目类别:
Continuing Grant
SHF: Small: Content-Aware Mapping of Streaming AI Workloads on Heterogeneous Edge Devices
SHF:小型:异构边缘设备上流式 AI 工作负载的内容感知映射
- 批准号:
2008244 - 财政年份:2020
- 资助金额:
$ 4.47万 - 项目类别:
Standard Grant
Planning IUCRC Arizona State University: Center for Networked Embedded, Smart and Trusted Things NESTT
规划 IUCRC 亚利桑那州立大学:网络嵌入式、智能和可信事物中心 NESTT
- 批准号:
1822169 - 财政年份:2018
- 资助金额:
$ 4.47万 - 项目类别:
Standard Grant
PFI:AIR - TT: Improving Robustness of Nanoscale Threshold Logic based Digitial Circuits and the Performance of Design Algorithms
PFI:AIR - TT:提高基于纳米级阈值逻辑的数字电路的鲁棒性和设计算法的性能
- 批准号:
1701241 - 财政年份:2017
- 资助金额:
$ 4.47万 - 项目类别:
Standard Grant
I-Corps: Sygnal: Compact, Low Power, High Performance Digital Circuits using Threshold Logic
I-Corps:Sygnal:使用阈值逻辑的紧凑、低功耗、高性能数字电路
- 批准号:
1565921 - 财政年份:2015
- 资助金额:
$ 4.47万 - 项目类别:
Standard Grant
I/UCRC FRP: Collaborative Research: Scalable and Power-Efficient Compressive Sensing CMOS Image Sensors and Reconstruction Circuits
I/UCRC FRP:合作研究:可扩展且节能的压缩传感 CMOS 图像传感器和重建电路
- 批准号:
1535669 - 财政年份:2015
- 资助金额:
$ 4.47万 - 项目类别:
Standard Grant
I/UCRC FRP: Collaborative Research: Testability and timing analysis in nanoscale designs in the presence of process variations
I/UCRC FRP:协作研究:存在工艺变化的纳米级设计中的可测试性和时序分析
- 批准号:
1432348 - 财政年份:2014
- 资助金额:
$ 4.47万 - 项目类别:
Standard Grant
I/UCRC: Consortium for Embedded Systems - Phase II
I/UCRC:嵌入式系统联盟 - 第二阶段
- 批准号:
1361926 - 财政年份:2014
- 资助金额:
$ 4.47万 - 项目类别:
Continuing Grant
I/UCRC: Collaborative Research: Synthesis and Design of Robust Threshold Logic Circuits
I/UCRC:合作研究:鲁棒阈值逻辑电路的综合与设计
- 批准号:
1230401 - 财政年份:2012
- 资助金额:
$ 4.47万 - 项目类别:
Standard Grant
PFI-BIC: Novel Circuit Architectures and Design Methodologies for Low Power Digital Systems
PFI-BIC:低功耗数字系统的新颖电路架构和设计方法
- 批准号:
1237856 - 财政年份:2012
- 资助金额:
$ 4.47万 - 项目类别:
Standard Grant
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