PFI:AIR - TT: Improving Robustness of Nanoscale Threshold Logic based Digitial Circuits and the Performance of Design Algorithms
PFI:AIR - TT:提高基于纳米级阈值逻辑的数字电路的鲁棒性和设计算法的性能
基本信息
- 批准号:1701241
- 负责人:
- 金额:$ 20万
- 依托单位:
- 依托单位国家:美国
- 项目类别:Standard Grant
- 财政年份:2017
- 资助国家:美国
- 起止时间:2017-07-15 至 2019-12-31
- 项目状态:已结题
- 来源:
- 关键词:
项目摘要
This PFI: AIR Technology Translation project focuses on translating a recent innovation of designing digital circuits with threshold-logic circuits to fill the need for achieving reductions in power consumption and size of digital systems, at advanced technology nodes. The threshold-logic circuits and the concomitant design methodology is important because, from a user's perspective, it will enable mobile systems such as laptops and smartphones to operate much longer between recharging of the batteries, and reduce their size and weight. It can also lead to reducing the energy usage of bigger systems such as desktop computers, and massive data centers. From a manufacturer's perspective, it can result in cost savings, improved reliability and more competitive products. The project will result in enhanced design tools, the design of threshold-logic primitive cells, and the design of a prototype circuit at least one advanced technology node to serve as a proof-of-concept of its robustness and scalability at lower geometries. This threshold-logic based digital design technology has the following unique features: (1) a new architecture and method of operation of certain digital circuit primitives, and (2) a new way of incorporating them automatically in larger circuits using existing design tools, i.e., without disrupting the existing design methodologies, so that it can be easily adopted by industry. These features provide the following advantages: smaller circuits, lower dynamic power consumption, lower standby power consumption, and lower variations in power, all without sacrificing speed, when compared to the leading competing digital ASIC (application specific integrated circuit) technology in this market space. This project addresses the following technology gap(s) as it translates from research discovery (successfully demonstrated at 65nm node) toward commercial application: the scalability of the technology and design methodology to advanced (smaller geometries- 40nm, 28nm) technology nodes, including overcoming physical design challenges, maintaining robustness to increased process variations, and scaling the accompanying software tools to industrial-scale circuits. These challenges will be addressed by first developing the circuit libraries in 40nm, which is still a key technology for many companies competing in the $1T IoT (internet of things) market, and then advancing to 28nm in FD-SOI. The performance and capability of the design software will be enhanced by developing better interfaces to existing commercial design tools, and use of faster software libraries and commercial software platforms. In addition, personnel involved in this project, Ph.D. level graduate students, will continue to receive significant training that requires developing a broad range of design and analytical skills, in multiple technical areas, as well as learning how to meet exacting industrial design standards. Other activities will include summer internships with companies that have expressed interest in the threshold-logic technology, visiting companies and presenting and marketing the research outcomes to industry.
该PFI:AIR技术翻译项目的重点是翻译最近的创新设计数字电路与阈值逻辑电路,以满足需要实现降低功耗和数字系统的大小,在先进的技术节点。 阈值逻辑电路和伴随的设计方法是重要的,因为从用户的角度来看,它将使移动的系统,如笔记本电脑和智能手机,以操作更长的时间之间的电池充电,并减少其尺寸和重量。它还可以减少台式计算机和大型数据中心等大型系统的能源使用。 从制造商的角度来看,它可以节省成本,提高可靠性和更具竞争力的产品。 该项目将导致增强的设计工具,阈值逻辑原始单元的设计,以及至少一个先进技术节点的原型电路的设计,以作为其在较低几何形状的鲁棒性和可扩展性的概念验证。这种基于阈值逻辑的数字设计技术具有以下独特的特征:(1)某些数字电路基元的新结构和操作方法,以及(2)使用现有设计工具将它们自动合并到较大电路中的新方法,即,而不会破坏现有的设计方法,因此它可以很容易地被工业采用。 这些特性提供了以下优势:更小的电路、更低的动态功耗、更低的待机功耗和更低的功率变化,与该市场领域领先的竞争数字ASIC(专用集成电路)技术相比,所有这些都不会牺牲速度。这个项目解决了以下技术差距,因为它从研究发现转化(在65 nm节点上成功演示)走向商业应用:技术和设计方法的可扩展性,(更小的几何形状-40纳米,28纳米)技术节点,包括克服物理设计挑战,保持鲁棒性增加工艺变化,并将附带的软件工具扩展到工业规模的电路。这些挑战将通过首先开发40纳米的电路库来解决,这仍然是许多公司在1 T物联网市场竞争的关键技术,然后在FD-SOI中推进到28纳米。 通过开发与现有商业设计工具更好的接口以及使用更快的软件库和商业软件平台,设计软件的性能和能力将得到增强。 此外,参与该项目的人员,博士。高级研究生将继续接受重要的培训,需要在多个技术领域发展广泛的设计和分析技能,并学习如何满足严格的工业设计标准。 其他活动将包括与对阈值逻辑技术感兴趣的公司进行暑期实习,访问公司并向行业展示和营销研究成果。
项目成果
期刊论文数量(5)
专著数量(0)
科研奖励数量(0)
会议论文数量(0)
专利数量(0)
FPGAs with Reconfigurable Threshold Logic Gates for Improved Performance, Power and Area
具有可重新配置阈值逻辑门的 FPGA,可提高性能、功耗和面积
- DOI:10.1109/fpl.2018.00051
- 发表时间:2018
- 期刊:
- 影响因子:0
- 作者:Wagle, Ankit;Yang, Jinghua;Dengi, Aykut;Vrudhula, Sarma
- 通讯作者:Vrudhula, Sarma
Design Considerations for Energy-Efficient and Variation-Tolerant Nonvolatile Logic
- DOI:10.1109/tvlsi.2018.2812700
- 发表时间:2018-03
- 期刊:
- 影响因子:2.8
- 作者:Jinghua Yang;A. Dengi;S. Vrudhula
- 通讯作者:Jinghua Yang;A. Dengi;S. Vrudhula
A Novel ASIC Design Flow Using Weight-Tunable Binary Neurons as Standard Cells
使用权重可调二元神经元作为标准单元的新型 ASIC 设计流程
- DOI:10.1109/tcsi.2022.3164995
- 发表时间:2022
- 期刊:
- 影响因子:0
- 作者:Wagle, Ankit;Singh, Gian;Khatri, Sunil;Vrudhula, Sarma
- 通讯作者:Vrudhula, Sarma
Embedding Binary Perceptrons in FPGA to improve Area, Power and Performance
在 FPGA 中嵌入二进制感知器以改善面积、功耗和性能
- DOI:10.1109/iccad45719.2019.8942071
- 发表时间:2019
- 期刊:
- 影响因子:0
- 作者:Wagle, Ankit;Azari, Elham;Vrudhula, Sarma
- 通讯作者:Vrudhula, Sarma
Threshold Logic in a Flash
瞬间阈值逻辑
- DOI:
- 发表时间:2019
- 期刊:
- 影响因子:0
- 作者:Ankit Wagle, Gian Singh
- 通讯作者:Ankit Wagle, Gian Singh
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Sarma Vrudhula其他文献
Thermal aware floorplanning incorporating temperature dependent wire delay estimation
- DOI:
10.1016/j.micpro.2015.09.013 - 发表时间:
2015-11-01 - 期刊:
- 影响因子:
- 作者:
Andreas Thor Winther;Wei Liu;Alberto Nannarelli;Sarma Vrudhula - 通讯作者:
Sarma Vrudhula
Sarma Vrudhula的其他文献
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{{ truncateString('Sarma Vrudhula', 18)}}的其他基金
IUCRC Phase I Arizona State University: Center for Intelligent, Distributed, Embedded, Applications and Systems (IDEAS)
IUCRC 第一阶段亚利桑那州立大学:智能、分布式、嵌入式、应用和系统中心 (IDEAS)
- 批准号:
2231620 - 财政年份:2023
- 资助金额:
$ 20万 - 项目类别:
Continuing Grant
SHF: Small: Content-Aware Mapping of Streaming AI Workloads on Heterogeneous Edge Devices
SHF:小型:异构边缘设备上流式 AI 工作负载的内容感知映射
- 批准号:
2008244 - 财政年份:2020
- 资助金额:
$ 20万 - 项目类别:
Standard Grant
Planning IUCRC Arizona State University: Center for Networked Embedded, Smart and Trusted Things NESTT
规划 IUCRC 亚利桑那州立大学:网络嵌入式、智能和可信事物中心 NESTT
- 批准号:
1822169 - 财政年份:2018
- 资助金额:
$ 20万 - 项目类别:
Standard Grant
I-Corps: Sygnal: Compact, Low Power, High Performance Digital Circuits using Threshold Logic
I-Corps:Sygnal:使用阈值逻辑的紧凑、低功耗、高性能数字电路
- 批准号:
1565921 - 财政年份:2015
- 资助金额:
$ 20万 - 项目类别:
Standard Grant
I/UCRC FRP: Collaborative Research: Scalable and Power-Efficient Compressive Sensing CMOS Image Sensors and Reconstruction Circuits
I/UCRC FRP:合作研究:可扩展且节能的压缩传感 CMOS 图像传感器和重建电路
- 批准号:
1535669 - 财政年份:2015
- 资助金额:
$ 20万 - 项目类别:
Standard Grant
I/UCRC FRP: Collaborative Research: Testability and timing analysis in nanoscale designs in the presence of process variations
I/UCRC FRP:协作研究:存在工艺变化的纳米级设计中的可测试性和时序分析
- 批准号:
1432348 - 财政年份:2014
- 资助金额:
$ 20万 - 项目类别:
Standard Grant
I/UCRC: Consortium for Embedded Systems - Phase II
I/UCRC:嵌入式系统联盟 - 第二阶段
- 批准号:
1361926 - 财政年份:2014
- 资助金额:
$ 20万 - 项目类别:
Continuing Grant
I/UCRC: Collaborative Research: Synthesis and Design of Robust Threshold Logic Circuits
I/UCRC:合作研究:鲁棒阈值逻辑电路的综合与设计
- 批准号:
1230401 - 财政年份:2012
- 资助金额:
$ 20万 - 项目类别:
Standard Grant
PFI-BIC: Novel Circuit Architectures and Design Methodologies for Low Power Digital Systems
PFI-BIC:低功耗数字系统的新颖电路架构和设计方法
- 批准号:
1237856 - 财政年份:2012
- 资助金额:
$ 20万 - 项目类别:
Standard Grant
NeTS:Medium:Collaborative Research: Exploiting Battery-Supply Nonlinearities in Optimal Resource Management and Protocol Design for Wireless Sensor Networks
NeTS:Medium:协作研究:在无线传感器网络的最佳资源管理和协议设计中利用电池电源非线性
- 批准号:
0905035 - 财政年份:2009
- 资助金额:
$ 20万 - 项目类别:
Standard Grant
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