PFI:AIR - TT: Improving Robustness of Nanoscale Threshold Logic based Digitial Circuits and the Performance of Design Algorithms

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This PFI: AIR Technology Translation project focuses on translating a recent innovation of designing digital circuits with threshold-logic circuits to fill the need for achieving reductions in power consumption and size of digital systems, at advanced technology nodes. The threshold-logic circuits and the concomitant design methodology is important because, from a user's perspective, it will enable mobile systems such as laptops and smartphones to operate much longer between recharging of the batteries, and reduce their size and weight. It can also lead to reducing the energy usage of bigger systems such as desktop computers, and massive data centers. From a manufacturer's perspective, it can result in cost savings, improved reliability and more competitive products. The project will result in enhanced design tools, the design of threshold-logic primitive cells, and the design of a prototype circuit at least one advanced technology node to serve as a proof-of-concept of its robustness and scalability at lower geometries. This threshold-logic based digital design technology has the following unique features: (1) a new architecture and method of operation of certain digital circuit primitives, and (2) a new way of incorporating them automatically in larger circuits using existing design tools, i.e., without disrupting the existing design methodologies, so that it can be easily adopted by industry. These features provide the following advantages: smaller circuits, lower dynamic power consumption, lower standby power consumption, and lower variations in power, all without sacrificing speed, when compared to the leading competing digital ASIC (application specific integrated circuit) technology in this market space. This project addresses the following technology gap(s) as it translates from research discovery (successfully demonstrated at 65nm node) toward commercial application: the scalability of the technology and design methodology to advanced (smaller geometries- 40nm, 28nm) technology nodes, including overcoming physical design challenges, maintaining robustness to increased process variations, and scaling the accompanying software tools to industrial-scale circuits. These challenges will be addressed by first developing the circuit libraries in 40nm, which is still a key technology for many companies competing in the $1T IoT (internet of things) market, and then advancing to 28nm in FD-SOI. The performance and capability of the design software will be enhanced by developing better interfaces to existing commercial design tools, and use of faster software libraries and commercial software platforms. In addition, personnel involved in this project, Ph.D. level graduate students, will continue to receive significant training that requires developing a broad range of design and analytical skills, in multiple technical areas, as well as learning how to meet exacting industrial design standards. Other activities will include summer internships with companies that have expressed interest in the threshold-logic technology, visiting companies and presenting and marketing the research outcomes to industry.