PFI:AIR - TT: Improving Robustness of Nanoscale Threshold Logic based Digitial Circuits and the Performance of Design Algorithms
PFI:AIR - TT: Improving Robustness of Nanoscale Threshold Logic based Digitial Circuits and the Performance of Design Algorithms
批准号:
1701241
负责人:
Sarma Vrudhula
金额:
$20.0万
依托单位:
依托单位国家:
美国
项目类别:
Standard Grant
财政年份:
2017
资助国家:
美国
项目状态:
已结题
起止时间:
2017-07-15 至 2019-12-31
中文摘要
这个PFI: AIR技术翻译项目的重点是翻译最新的数字电路设计创新与阈值逻辑电路,以满足在先进技术节点上实现降低功耗和数字系统尺寸的需求。阈值逻辑电路和伴随的设计方法很重要,因为从用户的角度来看,它将使笔记本电脑和智能手机等移动系统在电池充电之间运行更长时间,并减小其尺寸和重量。它还可以减少大型系统(如台式电脑和大型数据中心)的能源消耗。从制造商的角度来看,它可以节省成本,提高可靠性和更具竞争力的产品。该项目将增强设计工具,设计阈值逻辑原始单元,并设计至少一个先进技术节点的原型电路,以证明其在较低几何形状下的稳健性和可扩展性。这种基于阈值逻辑的数字设计技术具有以下独特的特点:(1)某些数字电路原语的新架构和操作方法;(2)使用现有设计工具自动将它们合并到更大的电路中的新方法,即不破坏现有的设计方法,因此它可以很容易地被工业采用。这些特性提供了以下优势:更小的电路,更低的动态功耗,更低的待机功耗和更低的功率变化,所有这些都不会牺牲速度,与领先的竞争数字ASIC(专用集成电路)技术相比,在这个市场空间。该项目解决了从研究发现(在65nm节点上成功演示)到商业应用的以下技术差距:技术和设计方法的可扩展性,以先进的(较小的几何形状- 40nm, 28nm)技术节点,包括克服物理设计挑战,保持对增加的工艺变化的稳健性,以及将配套的软件工具扩展到工业规模电路。这些挑战将首先通过开发40nm的电路库来解决,这仍然是许多公司在1万亿美元的物联网市场上竞争的关键技术,然后在FD-SOI中推进到28nm。通过开发与现有商业设计工具的更好接口,以及使用更快的软件库和商业软件平台,设计软件的性能和能力将得到提高。此外,参与该项目的博士研究生将继续接受重要的培训,这需要在多个技术领域发展广泛的设计和分析技能,以及学习如何满足严格的工业设计标准。其他活动包括在对阈值逻辑技术感兴趣的公司进行暑期实习,访问公司并向行业展示和营销研究成果。
英文摘要
This PFI: AIR Technology Translation project focuses on translating a recent innovation of designing digital circuits with threshold-logic circuits to fill the need for achieving reductions in power consumption and size of digital systems, at advanced technology nodes. The threshold-logic circuits and the concomitant design methodology is important because, from a user's perspective, it will enable mobile systems such as laptops and smartphones to operate much longer between recharging of the batteries, and reduce their size and weight. It can also lead to reducing the energy usage of bigger systems such as desktop computers, and massive data centers. From a manufacturer's perspective, it can result in cost savings, improved reliability and more competitive products. The project will result in enhanced design tools, the design of threshold-logic primitive cells, and the design of a prototype circuit at least one advanced technology node to serve as a proof-of-concept of its robustness and scalability at lower geometries. This threshold-logic based digital design technology has the following unique features: (1) a new architecture and method of operation of certain digital circuit primitives, and (2) a new way of incorporating them automatically in larger circuits using existing design tools, i.e., without disrupting the existing design methodologies, so that it can be easily adopted by industry. These features provide the following advantages: smaller circuits, lower dynamic power consumption, lower standby power consumption, and lower variations in power, all without sacrificing speed, when compared to the leading competing digital ASIC (application specific integrated circuit) technology in this market space. This project addresses the following technology gap(s) as it translates from research discovery (successfully demonstrated at 65nm node) toward commercial application: the scalability of the technology and design methodology to advanced (smaller geometries- 40nm, 28nm) technology nodes, including overcoming physical design challenges, maintaining robustness to increased process variations, and scaling the accompanying software tools to industrial-scale circuits. These challenges will be addressed by first developing the circuit libraries in 40nm, which is still a key technology for many companies competing in the $1T IoT (internet of things) market, and then advancing to 28nm in FD-SOI. The performance and capability of the design software will be enhanced by developing better interfaces to existing commercial design tools, and use of faster software libraries and commercial software platforms. In addition, personnel involved in this project, Ph.D. level graduate students, will continue to receive significant training that requires developing a broad range of design and analytical skills, in multiple technical areas, as well as learning how to meet exacting industrial design standards. Other activities will include summer internships with companies that have expressed interest in the threshold-logic technology, visiting companies and presenting and marketing the research outcomes to industry.
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FPGAs with Reconfigurable Threshold Logic Gates for Improved Performance, Power and Area
具有可重新配置阈值逻辑门的 FPGA,可提高性能、功耗和面积
DOI:
10.1109/fpl.2018.00051
发表时间:
2018
期刊:
Field Programmable Logic
影响因子:
--
作者:
[Wagle, Ankit, Yang, Jinghua, Dengi, Aykut, Vrudhula, Sarma]
通讯作者:
Vrudhula, Sarma
DOI:
10.1109/tvlsi.2018.2812700
发表时间:
2018-03
期刊:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
影响因子:
2.8
作者:
[Jinghua Yang;A. Dengi;S. Vrudhula]
通讯作者:
Jinghua Yang;A. Dengi;S. Vrudhula
A Novel ASIC Design Flow Using Weight-Tunable Binary Neurons as Standard Cells
使用权重可调二元神经元作为标准单元的新型 ASIC 设计流程
DOI:
10.1109/tcsi.2022.3164995
发表时间:
2022
期刊:
IEEE Transactions on Circuits and Systems I: Regular Papers
影响因子:
--
作者:
[Wagle, Ankit, Singh, Gian, Khatri, Sunil, Vrudhula, Sarma]
通讯作者:
Vrudhula, Sarma
Embedding Binary Perceptrons in FPGA to improve Area, Power and Performance
在 FPGA 中嵌入二进制感知器以改善面积、功耗和性能
DOI:
10.1109/iccad45719.2019.8942071
发表时间:
2019
期刊:
International Conference on Computer-Aided Design
影响因子:
--
作者:
[Wagle, Ankit, Azari, Elham, Vrudhula, Sarma]
通讯作者:
Vrudhula, Sarma
Threshold Logic in a Flash
瞬间阈值逻辑
DOI:
--
发表时间:
2019
期刊:
38th IEEE International Conference on Computer Design
影响因子:
--
作者:
[Ankit Wagle, Gian Singh]
通讯作者:
Ankit Wagle, Gian Singh
IUCRC Phase I Arizona State University: Center for Intelligent, Distributed, Embedded, Applications and Systems (IDEAS)
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批准号:2231620
-
项目类别:Continuing Grant
-
资助金额:$102.98万
-
财政年份:2023
-
负责人:Sarma Vrudhula
-
依托单位:
SHF: Small: Content-Aware Mapping of Streaming AI Workloads on Heterogeneous Edge Devices
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批准号:2008244
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项目类别:Standard Grant
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资助金额:$49.83万
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财政年份:2020
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负责人:Sarma Vrudhula
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依托单位:
Planning IUCRC Arizona State University: Center for Networked Embedded, Smart and Trusted Things NESTT
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批准号:1822169
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项目类别:Standard Grant
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资助金额:$1.5万
-
财政年份:2018
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负责人:Sarma Vrudhula
-
依托单位:
I-Corps: Sygnal: Compact, Low Power, High Performance Digital Circuits using Threshold Logic
-
批准号:1565921
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项目类别:Standard Grant
-
资助金额:$5.0万
-
财政年份:2015
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负责人:Sarma Vrudhula
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依托单位:
I/UCRC FRP: Collaborative Research: Scalable and Power-Efficient Compressive Sensing CMOS Image Sensors and Reconstruction Circuits
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批准号:1535669
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项目类别:Standard Grant
-
资助金额:$10.0万
-
财政年份:2015
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负责人:Sarma Vrudhula
-
依托单位:
I/UCRC FRP: Collaborative Research: Testability and timing analysis in nanoscale designs in the presence of process variations
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批准号:1432348
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项目类别:Standard Grant
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资助金额:$10.0万
-
财政年份:2014
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负责人:Sarma Vrudhula
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依托单位:
I/UCRC: Consortium for Embedded Systems - Phase II
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批准号:1361926
-
项目类别:Continuing Grant
-
资助金额:$35.27万
-
财政年份:2014
-
负责人:Sarma Vrudhula
-
依托单位:
I/UCRC: Collaborative Research: Synthesis and Design of Robust Threshold Logic Circuits
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批准号:1230401
-
项目类别:Standard Grant
-
资助金额:$10.0万
-
财政年份:2012
-
负责人:Sarma Vrudhula
-
依托单位:
PFI-BIC: Novel Circuit Architectures and Design Methodologies for Low Power Digital Systems
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批准号:1237856
-
项目类别:Standard Grant
-
资助金额:$60.0万
-
财政年份:2012
-
负责人:Sarma Vrudhula
-
依托单位:
NeTS:Medium:Collaborative Research: Exploiting Battery-Supply Nonlinearities in Optimal Resource Management and Protocol Design for Wireless Sensor Networks
-
批准号:0905035
-
项目类别:Standard Grant
-
资助金额:$21.5万
-
财政年份:2009
-
负责人:Sarma Vrudhula
-
依托单位:
Collaborative Research: Consortium for Embedded Systems
-
批准号:0856090
-
项目类别:Continuing Grant
-
资助金额:$30.0万
-
财政年份:2009
-
负责人:Sarma Vrudhula
-
依托单位:
Collaborative Research: Synthesis, Verification and Testing for Nano-CMOS and Beyond using Threshold Logic
-
批准号:0702831
-
项目类别:Standard Grant
-
资助金额:$20.0万
-
财政年份:2007
-
负责人:Sarma Vrudhula
-
依托单位:
Collaborative Research: Consortium for Embedded Systems
-
批准号:0700910
-
项目类别:Standard Grant
-
资助金额:$1.0万
-
财政年份:2007
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负责人:Sarma Vrudhula
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依托单位:
A Development System for Rapid Prototyping of Dynamically Reconfigurable Mixed-Signal Low-Power Systems
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批准号:9815615
-
项目类别:Standard Grant
-
资助金额:$25.0万
-
财政年份:1998
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负责人:Sarma Vrudhula
-
依托单位:
Center for Low Power Electronics
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批准号:9523338
-
项目类别:Cooperative Agreement
-
资助金额:$158.13万
-
财政年份:1996
-
负责人:Sarma Vrudhula
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依托单位:
An Undergraduate Digital Systems Laboratory With Emphasis OnVLSI
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批准号:9351291
-
项目类别:Standard Grant
-
资助金额:$4.47万
-
财政年份:1993
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负责人:Sarma Vrudhula
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依托单位:
RIA: Stochastic Models in Partitioning for Testability of Digital Circuits
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批准号:9296277
-
项目类别:Standard Grant
-
资助金额:$2.48万
-
财政年份:1992
-
负责人:Sarma Vrudhula
-
依托单位:
RIA: Stochastic Models in Partitioning for Testability of Digital Circuits
-
批准号:9111206
-
项目类别:Standard Grant
-
资助金额:$3.52万
-
财政年份:1991
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负责人:Sarma Vrudhula
-
依托单位:
国内基金
海外基金
湍流和化学交互作用对H2-Air-H2O微混燃烧中NO生成的影响研究
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批准号:51976048
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项目类别:面上项目
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资助金额:61.0万元
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批准年份:2019
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负责人:邱朋华
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依托单位: