CRII: SHF: Investigation of Effective On-chip Network Designs for GPUs

在过去的十年中，图形处理单元(GPU)以惊人的速度激增。相关技术的持续创新使今天的S图形处理器能够在众多学科和行业以及许多新兴领域发挥关键作用，否则这些领域可能无法实现。例如，处理汽车中的环境视频输入以增强安全性和智能驾驶；支持移动设备中基于图形的医疗处理应用，以实现无处不在的生物识别监控和个性化医疗保健；支持虚拟现实耳机，以实现教育、培训和娱乐中变革性和身临其境的新体验；以及在高性能计算系统和数据中心中提供高能效并行计算，以促进无数科学、经济和社会计算应用。如此有前景的发展得益于GPU架构的大规模并行计算能力，它可以在一块芯片上集成数千个处理核心。为了继续满足日益增长的性能期望，必须开发片上互连体系结构以在GPU中的大量处理核之间提供快速高效的通信。其目标是充分探索挑战，并开发适用于GPU NoC设计的框架，以满足当前和未来GPU系统的性能、能源和资源效率目标。调查的一些具体方面包括：GPU环境中NoC的瓶颈、支持向上扩展的替代方法、NoC对各种类型的GPU应用程序的敏感性，以及NoC对GPU系统级权衡的影响。这项研究还调查了NoC组件之间的协调设计机会，以及NoC和其他GPU子系统之间的协同优化。其目标是通过考虑多个组件和关键应用程序特性，使片上网络能够更一致、更高效地运行，从而为GPU系统的整体利益服务。这项研究除了对计算机的基本进步作出具体的技术贡献外，还通过其研究、教育和推广活动对社会产生更广泛的潜在影响，这些活动旨在扩大不同背景的人的参与，包括在不同教育水平的工程学代表不足的群体。

Graphics Processing Units (GPUs) have been proliferating at an extraordinary speed in the past decade. Continuing innovations in related technologies allow today?s GPUs to play critical roles in numerous disciplines and sectors as well as many emerging fields that might not otherwise be possible. Examples include processing ambient video inputs in automobiles for enhanced safety and intelligent driving; powering graphics-based medical processing applications in mobile devices for ubiquitous biometric monitoring and personalized healthcare; supporting virtual reality headsets for transformative and immersive new experiences in education, training, and entertainment; and providing energy-efficient parallel computing in HPC systems and data-centers to facilitate a myriad of scientific, economic, and social computing applications. Such promising developments are enabled by the massively parallel computing capacity of GPU architectures, which can integrate thousands of processing cores on a single chip. To continue meeting growing performance expectations, on-chip interconnect architectures must be developed to provide fast and efficient communications among the vast number of processing cores in GPUs.This research investigates cross-cutting approaches and techniques to improve the effectiveness of on-chip networks (or NoCs) in GPU systems. The objective is to fully explore the challenges and develop framework useful for GPU NoC designs that will meet the performance, energy, and resource efficiency targets of current and future GPU systems. Among some of the specific aspects investigated are the bottlenecks of NoCs in the GPU context, alternative methods of enabling scale-up, sensitivity of NoCs to various types of GPU applications, and the impact of NoCs on GPU system-level trade-offs. This research also investigates opportunities in coordinated design among NoC components as well as co-optimizations between NoCs and other GPU subsystems. The objective is to enable on-chip networks to operate more consistently and efficiently for the overall benefit of GPU systems by factoring in multiple components and key application characteristics. Beyond its specific technical contributions to fundamental advancements in computing, this research has broader potential impact to society through its activities on research education and outreach that aim to broaden participation for people from diverse background, including groups underrepresented in engineering at various education levels.