CRII: SHF: Investigation of Effective On-chip Network Designs for GPUs

图形处理单元（GPU）在过去十年中以惊人的速度激增。相关技术的不断创新使今天？的GPU在众多学科和领域以及许多新兴领域发挥着至关重要的作用，否则可能无法实现。示例包括处理汽车中的环境视频输入以增强安全性和智能驾驶;为移动的设备中基于图形的医疗处理应用提供动力，以实现无处不在的生物特征监测和个性化医疗保健;支持虚拟现实耳机，以实现教育、培训和娱乐方面的变革性和沉浸式新体验;并在HPC系统和数据中心中提供高能效并行计算，以促进无数科学、经济和社会计算应用。这些有前途的发展是由GPU架构的大规模并行计算能力实现的，GPU架构可以在单个芯片上集成数千个处理核心。为了继续满足不断增长的性能期望，必须开发片上互连架构，以便在GPU中的大量处理核心之间提供快速有效的通信。本研究探讨了提高GPU系统中片上网络（或NoC）有效性的交叉方法和技术。我们的目标是充分探索挑战，并为GPU NoC设计开发有用的框架，以满足当前和未来GPU系统的性能，能源和资源效率目标。其中一些具体方面的调查是在GPU的情况下，使规模扩大的替代方法，NoC的各种类型的GPU应用程序的敏感性，以及NoC的GPU系统级权衡的影响NoC的瓶颈。本研究还探讨了NoC组件之间的协调设计以及NoC与其他GPU子系统之间的协同优化的机会。其目标是通过考虑多个组件和关键应用特性，使片上网络能够更一致、更高效地运行，从而为GPU系统带来整体效益。除了对计算基础进步的具体技术贡献外，这项研究还通过其研究教育和推广活动对社会产生了更广泛的潜在影响，这些活动旨在扩大来自不同背景的人的参与，包括在各种教育水平的工程中代表性不足的群体。

Graphics Processing Units (GPUs) have been proliferating at an extraordinary speed in the past decade. Continuing innovations in related technologies allow today?s GPUs to play critical roles in numerous disciplines and sectors as well as many emerging fields that might not otherwise be possible. Examples include processing ambient video inputs in automobiles for enhanced safety and intelligent driving; powering graphics-based medical processing applications in mobile devices for ubiquitous biometric monitoring and personalized healthcare; supporting virtual reality headsets for transformative and immersive new experiences in education, training, and entertainment; and providing energy-efficient parallel computing in HPC systems and data-centers to facilitate a myriad of scientific, economic, and social computing applications. Such promising developments are enabled by the massively parallel computing capacity of GPU architectures, which can integrate thousands of processing cores on a single chip. To continue meeting growing performance expectations, on-chip interconnect architectures must be developed to provide fast and efficient communications among the vast number of processing cores in GPUs.This research investigates cross-cutting approaches and techniques to improve the effectiveness of on-chip networks (or NoCs) in GPU systems. The objective is to fully explore the challenges and develop framework useful for GPU NoC designs that will meet the performance, energy, and resource efficiency targets of current and future GPU systems. Among some of the specific aspects investigated are the bottlenecks of NoCs in the GPU context, alternative methods of enabling scale-up, sensitivity of NoCs to various types of GPU applications, and the impact of NoCs on GPU system-level trade-offs. This research also investigates opportunities in coordinated design among NoC components as well as co-optimizations between NoCs and other GPU subsystems. The objective is to enable on-chip networks to operate more consistently and efficiently for the overall benefit of GPU systems by factoring in multiple components and key application characteristics. Beyond its specific technical contributions to fundamental advancements in computing, this research has broader potential impact to society through its activities on research education and outreach that aim to broaden participation for people from diverse background, including groups underrepresented in engineering at various education levels.