CAREER: Advancing On-chip Network Architecture for GPUs

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Graphics Processing Units (GPUs) have been playing critical roles in numerous disciplines and sectors, as well as many emerging fields that might not otherwise be possible. Examples include autonomous driving, virtual reality, medical imaging, and parallel computing in HPC systems and data-centers. This success should be largely credited to the massively parallel computing capability of GPU architectures, which can integrate thousands of processing cores on a single chip. To continue meeting growing performance expectations and energy-efficiency, a key challenge over the next decade and beyond is how to support on-chip communications among the vast number of processing cores and provide fast and efficient data transfer to feed concurrent computations.This project establishes an integrated research and education program to investigate cross-cutting approaches and techniques to advance and improve the effectiveness of on-chip networks (NoCs) in GPU systems, as well as to create academic course materials and outreach activities for the education and broad dissemination of the proposed subjects. The research component has three main thrusts: 1) increasing fundamental understanding of GPU NoCs by investigating, among many other open problems, the criticality, scalability and sensitivity of NoCs to GPU architecture; 2) designing and implementing cost-effective router-based and routerless GPU NoCs, and 3) co-optimizing NoC design with other GPU subsystems such as cache and warp scheduling. The education and outreach components include developing automated tools to increase the effectiveness of simulation-based course projects and engage students from diverse backgrounds, strengthening architecture course offerings, organizing interdisciplinary seminar courses, and leading various outreach activities on K-12 education, women and underrepresented groups.