Combating Counterfeit Analog and Mixed Signal ICs with Lightweight Embedded Mechanisms and Innovative Electrical Tests

提案标题：利用轻量级嵌入式机制和创新电气测试打击假冒模拟和混合信号 IC 项目目标简要说明：以有针对性的电气测试和设计结构为中心的检测和避免模拟和混合信号假冒 IC 的综合框架。非技术摘要：全球化导致整个供应链中报告的各类假冒电子元件数量大幅增加。除了知识产权侵权造成的数十亿美元损失之外，假冒零件通常质量不合格，从而给包含这些零件的关键系统和基础设施带来风险。在集成电路 (IC) 中，模拟和混合信号 (AMS) IC 因其产品生命周期长、利润率高、在主要市场（工业、汽车、智能、消费类、无线、计算等）的普及、复杂性较低以及 (v) 易于逆向工程和克隆旧工艺技术节点而成为假冒的最佳目标。鉴于大量系统和行业使用 AMS 电子产品，假冒产品对主要零部件制造商、原始设备制造商、政府和社会产生了重大影响。虽然存在可应用于 AMS IC 的基于物理检查和电气测试的伪造品检测方法，但它们非常耗时、具有破坏性，并且通常需要黄金（已知真实）信息。此外，已经开发出新的设计技术来检测假冒数字 IC，但由于模拟和数字设计之间的根本差异，这些技术不太适合 AMS IC。技术摘要：该项目首次探索了一个整体框架来检测和防止所有类型的模拟和混合信号 (AMS) 假冒 IC。这一目标的根本挑战包括缺乏老化模型（检测回收/使用过的 IC 所需）、缺乏数字 IC 功能（例如测试结构、传统密码模块等）以及 AMS IC 的严格资源限制。在这项工作中，这些挑战通过开发用于检测回收和标记 IC 的创新电气测试以及开发用于检测/预防克隆、过度生产和回收 IC 的轻量级嵌入式机制来解决。为了消除对黄金信息的需求并保持适用于各种 IC，电气测试针对通用电源管理电路的行为差异，这些电路可在许多大型模拟、混合信号和数字 IC 中访问，例如低压差稳压器 (LDO)。用于无源 IC 仿冒检测的嵌入式机制是基于完全模拟物理不可克隆功能 (PUF) 和新的回收\老化传感器而开发的。虽然现有机制需要数字控制逻辑和额外的引脚来访问 PUF 和传感器输出，但开发了新的低成本接口以使所有提议的方法更容易采用。为了主动预防，混沌密码学（可以在模拟 IC 中实现）被用于新颖的 IC 锁定\解锁机制，以防止过量生产的 IC 进入市场。所有方法都将在模拟和硅中进行测试。 PI 实验室将从行业合作者处获取正品 IC，并对其进行测试以防止假冒。嵌入式机制将被纳入测试 IC 中，并使用标准 CMOS 工艺制造以进行验证。

Proposal Title: Combating Counterfeit Analog and Mixed Signal ICs with Lightweight Embedded Mechanisms and Innovative Electrical Tests Brief description of project Goals: A comprehensive framework for detecting and avoiding analog and mixed signal counterfeit ICs centered on targeted electrical tests and design structures.Nontechnical Abstract:Globalization has resulted in a substantial rise in all types of counterfeit electronic components reported throughout the supply chain. Aside from the billions lost from IP infringement, counterfeit parts are often of substandard quality, thereby creating risks for the critical systems and infrastructures that incorporate them. Among integrated circuits (ICs), analog and mixed signal (AMS) ICs are the best targets for counterfeiting due to their long product life cycles, high profit margins, prevalence across major markets (industrial, automotive, intelligence, consumer, wireless, compute, etc.), lower complexity, and (v) ease of reverse engineering and cloning older process technology nodes. Given the large number of systems and sectors using AMS electronics, counterfeits have significant impacts on major component manufacturers, original equipment manufacturers, governments, and society. While there exist counterfeit detection approaches based on physical inspection and electrical tests that could be applied to AMS ICs, they are time consuming, destructive, and often require golden (known authentic) information. In addition, new design techniques have been developed to detect counterfeit digital ICs, but these are not well-suited for AMS ICs due to the fundamental differences between analog and digital design. Technical Abstract:This project explores, for the first time, a holistic framework to detect and prevent all types of analog and mixed-signal (AMS) counterfeit ICs. Fundamental challenges to this goal include lack of aging models (needed to detect recycled/used ICs), lack of digital IC features (e.g., test structures, traditional cryptographic modules, etc.), and strict resource constraints of AMS ICs. In this work, these challenges are addressed through the development of innovative electrical tests for detecting recycled and remarked ICs as well as development of lightweight embedded mechanisms for detection/prevention of cloned, overproduced, and recycled ICs. To eliminate the need for golden information and remain applicable to a wide range of ICs, the electrical tests target differences in behavior of general power management circuitry, which are accessible in many large analog, mixed signal, and digital ICs, such as Low Drop-Out Regulators (LDOs) Embedded mechanisms for passive IC counterfeit detection are developed based on fully analog physically unclonable functions (PUFs) and new recycling\aging sensors. While existing mechanisms require digital control logic and an additional pin for access to PUF and sensor output, new low cost-interfaces are developed to make all the proposed approaches easier to adopt. For active prevention, chaotic cryptography (which can be implemented in analog ICs) is exploited for novel IC locking\unlocking mechanisms that prevent overproduced ICs from entering the market. All approaches will be tested in simulation and silicon. Authentic ICs will be acquired and tested against counterfeits available in the PI's lab from industry collaborators. The embedded mechanisms will be incorporated into test ICs and fabricated using standard CMOS processes for validation.