STARSS: Small: Collaborative: Physical Design for Secure Split Manufacturing of ICs

STARSS：小型：协作：IC 安全分割制造的物理设计

• 批准号: 1618797
• 负责人: Jeyavijayan Rajendran
• 金额: $ 15.33万
• 依托单位: University of Texas at Dallas
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2016
• 资助国家: 美国
• 起止时间: 2016-10-01 至 2018-02-28
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=1618797&HistoricalAwards=false
• 关键词: STARSS; Small; Collaborative; Physical; Design

The trend of outsourcing semiconductor manufacturing to oversea foundries has introduced several security vulnerabilities -- reverse engineering, malicious circuit insertion, counterfeiting, and intellectual property piracy -- making the semiconductor industry lose billions of dollars. Split manufacturing of integrated circuits reduces vulnerabilities introduced by an untrusted foundry by manufacturing only some of the layers at an untrusted high-end foundry and the remaining layers at a trusted low-end foundry. An attacker in the untrusted foundry has access only to an incomplete design, and therefore cannot easily pirate or insert Trojans into it. However, split manufacturing alone is not sufficiently secure, and naïve security enhancement techniques incur tremendous power, area, and delay overhead. The goal of this research is to develop new physical-design techniques that can ensure security through split manufacturing and simultaneously minimize the overhead on performance, power and area of semiconductor products.This research lays the foundations for a comprehensive set of physical design tools for security. Its expected outcomes are: 1) Systematic techniques for modeling attacks that recover the missing parts of the design from the information available to the attacker; 2) Security metrics to assess the strength of integrated circuit designs by measuring the difficulty for an attacker to reverse engineer the design in the context of split manufacturing; 3) Active defenses through physical designs techniques such as cell layout, placement perturbation and rerouting designs to increase security; 4) Techniques to reduce the overhead of secure split manufacturing and make the security enhancement seamlessly compatible with existing design flows.

将半导体制造与海外铸造厂外包给外国铸造厂的趋势引入了一些安全漏洞 - 反向工程，恶意巡回赛插入，伪造和知识产权盗版 - 使半导体行业损失了数十亿美元。综合电路的拆分制造可以减少不受信任的铸造厂引入的漏洞，仅在不信任的高端铸造厂和值得信赖的低端铸造厂的其余层中仅生产某些层。不受信任的铸造厂中的攻击者只能访问不完整的设计，因此无法轻易盗版或将特洛伊木马插入其中。但是，仅分裂制造业并不足够安全，并且幼稚的安全增强技术会产生巨大的力量，区域和延迟开销。这项研究的目的是开发新的物理设计技术，这些技术可以通过分裂制造来确保安全性，并简单地最大程度地减少半导体产品的性能，功率和领域的开销。这项研究为一套全面的物理设计工具提供了基础，以确保安全。它的预期结果是：1）用于建模攻击的系统技术，这些技术可从攻击者可用的信息中恢复设计的缺失部分； 2）通过测量攻击者在拆分制造的背景下对设计的难度来评估综合电路设计的强度的安全指标； 3）通过物理设计技术的主动防御能力，例如细胞布局，放置扰动和重新路由设计，以提高安全性； 4）减少安全拆分制造的开销的技术，并使安全增强与现有设计流无缝兼容。