STARSS: Small: Collaborative: Physical Design for Secure Split Manufacturing of ICs

将半导体制造外包给海外代工厂的趋势带来了几个安全漏洞--反向工程、恶意电路插入、假冒和知识产权盗版--使半导体行业损失数十亿美元。集成电路的拆分制造通过在不可信的高端铸造厂只制造部分层，而在可信的低端铸造厂制造剩余的层来减少由不可信的铸造厂引入的脆弱性。不受信任的铸造厂中的攻击者只能访问不完整的设计，因此不能轻松地盗版或向其中插入特洛伊木马程序。然而，单靠拆分制造是不够安全的，幼稚的安全增强技术会带来巨大的功耗、面积和延迟开销。这项研究的目标是开发新的物理设计技术，通过分离制造来确保安全性，同时将半导体产品在性能、功耗和面积上的开销降至最低，为一套全面的安全物理设计工具奠定基础。它的预期结果是：1)系统的攻击建模技术，从攻击者可用的信息中恢复设计的缺失部分；2)安全度量，通过测量攻击者在拆分制造环境中对设计进行逆向工程的难度来评估集成电路设计的强度；3)通过物理设计技术(如单元布局、布局扰动和重新布线设计)进行主动防御，以提高安全性；4)减少安全拆分制造的开销并使安全增强与现有设计流程无缝兼容的技术。

The trend of outsourcing semiconductor manufacturing to oversea foundries has introduced several security vulnerabilities -- reverse engineering, malicious circuit insertion, counterfeiting, and intellectual property piracy -- making the semiconductor industry lose billions of dollars. Split manufacturing of integrated circuits reduces vulnerabilities introduced by an untrusted foundry by manufacturing only some of the layers at an untrusted high-end foundry and the remaining layers at a trusted low-end foundry. An attacker in the untrusted foundry has access only to an incomplete design, and therefore cannot easily pirate or insert Trojans into it. However, split manufacturing alone is not sufficiently secure, and naïve security enhancement techniques incur tremendous power, area, and delay overhead. The goal of this research is to develop new physical-design techniques that can ensure security through split manufacturing and simultaneously minimize the overhead on performance, power and area of semiconductor products.This research lays the foundations for a comprehensive set of physical design tools for security. Its expected outcomes are: 1) Systematic techniques for modeling attacks that recover the missing parts of the design from the information available to the attacker; 2) Security metrics to assess the strength of integrated circuit designs by measuring the difficulty for an attacker to reverse engineer the design in the context of split manufacturing; 3) Active defenses through physical designs techniques such as cell layout, placement perturbation and rerouting designs to increase security; 4) Techniques to reduce the overhead of secure split manufacturing and make the security enhancement seamlessly compatible with existing design flows.