CAREER: Towards Provably-Secure Design of Integrated Circuits

近年来，计算机芯片的生产普遍向海外转移，降低了设计复杂性和制造成本。但这些好处是以牺牲安全性为代价的：供应链上任何地方的攻击都可以将恶意组件插入集成电路，盗版其设计或伪造它。这些极其难以察觉的攻击危及计算机行业，破坏国家安全，并将关键基础设施置于危险之中。对硬件安全的十多年研究已经产生了针对这些问题的大量解决方案，但其中许多解决方案针对的是特定的攻击模型，因此并不普遍适用。该项目通过开发硬件设计方法打破了这一障碍，这些方法既可证明是安全的，又适用于整个硬件行业的不同业务和威胁模型。为了吸引和教育下一代网络安全专家，该项目在高中、本科和研究生阶段采用谜题、挑战和竞争为基础的教育和推广活动。该项目有三个组成部分。首先，该研究开发了一种安全的综合方法，使用可证明的安全伪装和逻辑加密来防止盗版和逆向工程，其中攻击者仅提供部分设计知识以混淆设计意图。其次，通过演示通过测试数据泄露机密的攻击，分析了不可信测试设施的安全含义。开发了一种可证明安全的测试模式生成技术，用于测试带有机密的芯片。第三，这个项目设计的芯片使得任何（恶意的）修改和伪造都可以被现有的技术检测到。

The production of computer chips has universally moved offshore in recent years, reducing design complexity and fabrication cost. But these benefits come at the expense of security: An attack anywhere along the supply chain can insert malicious components into an integrated circuit, pirate its design or counterfeit it. These attacks, which are exceedingly difficult to detect, jeopardize the computer industry, undermine national security, and put critical infrastructure in danger. More than a decade of research in hardware security has resulted in a plethora of solutions for these problems, but many of these solutions address specific attack models and, hence, are not universally applicable. This project breaks this barrier by developing hardware design approaches that are both provably secure and applicable across the entire hardware industry for differing businesses and threat models. To engage and teach the next generation of cybersecurity experts, the project uses puzzle-, challenge-, and competition-based educational and outreach activities at the high-school, undergraduate, and graduate levels. The project has three components. First, the research develops a secure synthesis approach to prevent piracy and reverse engineering using provably-secure camouflaging and logic encryption, where the attacker is provided with only partial knowledge of the design to obfuscate the design intent. Second, the research analyzes the security implications of untrusted test facilities by demonstrating an attack to compromise secrets through test data. It develops a provably-secure test pattern generation technique for testing chips with secrets. Third, this project designs chips such that any (malicious) alterations and counterfeits are provably-detected by existing techniques.