CAREER: Towards Provably-Secure Design of Integrated Circuits
CAREER: Towards Provably-Secure Design of Integrated Circuits
批准号:
1822848
负责人:
Jeyavijayan Rajendran
金额:
$48.09万
依托单位国家:
美国
项目类别:
Continuing Grant
财政年份:
2017
资助国家:
美国
项目状态:
已结题
起止时间:
2017-09-01 至 2024-01-31
中文摘要
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英文摘要
The production of computer chips has universally moved offshore in recent years, reducing design complexity and fabrication cost. But these benefits come at the expense of security: An attack anywhere along the supply chain can insert malicious components into an integrated circuit, pirate its design or counterfeit it. These attacks, which are exceedingly difficult to detect, jeopardize the computer industry, undermine national security, and put critical infrastructure in danger. More than a decade of research in hardware security has resulted in a plethora of solutions for these problems, but many of these solutions address specific attack models and, hence, are not universally applicable. This project breaks this barrier by developing hardware design approaches that are both provably secure and applicable across the entire hardware industry for differing businesses and threat models. To engage and teach the next generation of cybersecurity experts, the project uses puzzle-, challenge-, and competition-based educational and outreach activities at the high-school, undergraduate, and graduate levels. The project has three components. First, the research develops a secure synthesis approach to prevent piracy and reverse engineering using provably-secure camouflaging and logic encryption, where the attacker is provided with only partial knowledge of the design to obfuscate the design intent. Second, the research analyzes the security implications of untrusted test facilities by demonstrating an attack to compromise secrets through test data. It develops a provably-secure test pattern generation technique for testing chips with secrets. Third, this project designs chips such that any (malicious) alterations and counterfeits are provably-detected by existing techniques.
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Towards Provably-Secure Analog and Mixed-Signal Locking Against Overproduction
迈向可证明安全的模拟和混合信号锁定,防止生产过剩
DOI:
10.1109/tetc.2020.3025561
发表时间:
2020
期刊:
IEEE Transactions on Emerging Topics in Computing
影响因子:
5.9
作者:
[GummidipoondiJayasankaran, Nithyashankari, Sanabria Borbon, Adriana, Sanchez Sinencio, Edgar, Hu, Jiang, Rajendran, Jeyavijayan]
通讯作者:
Rajendran, Jeyavijayan
Reinforcement Learning for Hardware Security: Opportunities, Developments, and Challenges
硬件安全的强化学习:机遇、发展和挑战
DOI:
10.1109/isocc56007.2022.10031569
发表时间:
2022
期刊:
IEEE International SoC Design Conference (ISOCC
影响因子:
--
作者:
[Patnaik, Satwik, Gohil, Vasudev, Guo, Hao, Rajendran, Jeyavijayan JV]
通讯作者:
Rajendran, Jeyavijayan JV
Thwarting Replication Attack against Memristor-based Neuromorphic Computing System
阻止针对基于忆阻器的神经形态计算系统的复制攻击
DOI:
10.1109/tcad.2019.2937817
发表时间:
2019
期刊:
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
影响因子:
2.9
作者:
[Yang, Chaofei, Liu, Beiye, Li, Hai, Chen, Yiran, Barnell, Mark, Wu, Qing, Wen, Wujie, Rajendran, Jeyavijayan]
通讯作者:
Rajendran, Jeyavijayan
DOI:
10.1109/tcad.2019.2944586
发表时间:
2020-10-01
期刊:
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS
影响因子:
2.9
作者:
[Chakraborty, Abhishek, Jayasankaran, Nithyashankari Gummidipoondi, Zuzak, Michael]
通讯作者:
Zuzak, Michael
DOI:
10.1109/tetc.2017.2740364
发表时间:
2020-04
期刊:
IEEE Transactions on Emerging Topics in Computing
影响因子:
5.9
作者:
[Muhammad Yasin;Bodhisatwa Mazumdar;O. Sinanoglu;Jeyavijayan Rajendran]
通讯作者:
Muhammad Yasin;Bodhisatwa Mazumdar;O. Sinanoglu;Jeyavijayan Rajendran
共 12 条
Collaborative Research: EAGER: SaTC-EDU: Dynamic Adaptive Machine Learning for Teaching Hardware Security (DYNAMITES)
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批准号:2039610
-
项目类别:Standard Grant
-
资助金额:$15.0万
-
财政年份:2020
-
负责人:Jeyavijayan Rajendran
-
依托单位:
EAGER: Collaborative: Secure and Trustworthy Cyberphysical Microfluidic Systems
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批准号:1833623
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项目类别:Standard Grant
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资助金额:$7.0万
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财政年份:2018
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负责人:Jeyavijayan Rajendran
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依托单位:
SHF:Small: OSCARS: Optimizing Self-Configurable Analog ICs for Reliability and Security
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批准号:1815583
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项目类别:Standard Grant
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资助金额:$40.0万
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财政年份:2018
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负责人:Jeyavijayan Rajendran
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依托单位:
CAREER: Towards Provably-Secure Design of Integrated Circuits
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批准号:1652842
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项目类别:Continuing Grant
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资助金额:$50.0万
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财政年份:2017
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负责人:Jeyavijayan Rajendran
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依托单位:
STARSS: Small: Collaborative: Physical Design for Secure Split Manufacturing of ICs
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批准号:1822840
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项目类别:Standard Grant
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资助金额:$9.59万
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财政年份:2017
-
负责人:Jeyavijayan Rajendran
-
依托单位:
STARSS: Small: Collaborative: Physical Design for Secure Split Manufacturing of ICs
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批准号:1618797
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项目类别:Standard Grant
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资助金额:$15.33万
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财政年份:2016
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负责人:Jeyavijayan Rajendran
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依托单位:
海外基金