CAREER: Towards Provably-Secure Design of Integrated Circuits

职业：迈向可证明安全的集成电路设计

• 批准号: 1822848
• 负责人: Jeyavijayan Rajendran
• 金额: $ 48.09万
• 依托单位: Texas A&M Engineering Experiment Station
• 依托单位国家: 美国
• 项目类别: Continuing Grant
• 财政年份: 2017
• 资助国家: 美国
• 起止时间: 2017-09-01 至 2024-01-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=1822848&HistoricalAwards=false
• 关键词: CAREER; Towards; Provably; Secure; Design

The production of computer chips has universally moved offshore in recent years, reducing design complexity and fabrication cost. But these benefits come at the expense of security: An attack anywhere along the supply chain can insert malicious components into an integrated circuit, pirate its design or counterfeit it. These attacks, which are exceedingly difficult to detect, jeopardize the computer industry, undermine national security, and put critical infrastructure in danger. More than a decade of research in hardware security has resulted in a plethora of solutions for these problems, but many of these solutions address specific attack models and, hence, are not universally applicable. This project breaks this barrier by developing hardware design approaches that are both provably secure and applicable across the entire hardware industry for differing businesses and threat models. To engage and teach the next generation of cybersecurity experts, the project uses puzzle-, challenge-, and competition-based educational and outreach activities at the high-school, undergraduate, and graduate levels. The project has three components. First, the research develops a secure synthesis approach to prevent piracy and reverse engineering using provably-secure camouflaging and logic encryption, where the attacker is provided with only partial knowledge of the design to obfuscate the design intent. Second, the research analyzes the security implications of untrusted test facilities by demonstrating an attack to compromise secrets through test data. It develops a provably-secure test pattern generation technique for testing chips with secrets. Third, this project designs chips such that any (malicious) alterations and counterfeits are provably-detected by existing techniques.

近年来，计算机芯片的生产普遍转移到了海外，降低了设计复杂性和制造成本。但这些好处是以牺牲安全为代价的：供应链上任何地方的攻击都可能将恶意元件插入集成电路，盗版其设计或假冒。这些极难发现的攻击危害了计算机行业，破坏了国家安全，并将关键基础设施置于危险之中。十多年来对硬件安全的研究已经为这些问题提供了过多的解决方案，但其中许多解决方案针对特定的攻击模型，因此并不是通用的。该项目通过开发可证明安全且适用于不同业务和威胁模型的整个硬件行业的硬件设计方法，打破了这一障碍。为了吸引和教授下一代网络安全专家，该项目在高中、本科生和研究生级别使用基于谜题、挑战和竞争的教育和推广活动。该项目有三个组成部分。首先，研究开发了一种安全的合成方法，使用可证明安全的伪装和逻辑加密来防止盗版和反向工程，其中攻击者只被提供了部分设计知识来混淆设计意图。其次，该研究通过演示通过测试数据泄露机密的攻击来分析不可信测试设备的安全影响。它开发了一种可证明安全的测试模式生成技术，用于测试带有秘密的芯片。第三，该项目设计的芯片可以通过现有技术检测到任何(恶意的)改动和假冒产品。

项目成果

Towards Provably-Secure Analog and Mixed-Signal Locking Against Overproduction

迈向可证明安全的模拟和混合信号锁定，防止生产过剩

• DOI: 10.1109/tetc.2020.3025561
• 发表时间: 2020
• 期刊: IEEE Transactions on Emerging Topics in Computing
• 影响因子: 5.9
• 作者: GummidipoondiJayasankaran, Nithyashankari;Sanabria Borbon, Adriana;Sanchez Sinencio, Edgar;Hu, Jiang;Rajendran, Jeyavijayan
• 通讯作者: Rajendran, Jeyavijayan

Reinforcement Learning for Hardware Security: Opportunities, Developments, and Challenges

硬件安全的强化学习：机遇、发展和挑战

• DOI: 10.1109/isocc56007.2022.10031569
• 发表时间: 2022
• 期刊: IEEE International SoC Design Conference (ISOCC
• 作者: Patnaik, Satwik;Gohil, Vasudev;Guo, Hao;Rajendran, Jeyavijayan JV
• 通讯作者: Rajendran, Jeyavijayan JV

Thwarting Replication Attack against Memristor-based Neuromorphic Computing System

阻止针对基于忆阻器的神经形态计算系统的复制攻击

• DOI: 10.1109/tcad.2019.2937817
• 发表时间: 2019
• 期刊: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
• 影响因子: 2.9
• 作者: Yang, Chaofei;Liu, Beiye;Li, Hai;Chen, Yiran;Barnell, Mark;Wu, Qing;Wen, Wujie;Rajendran, Jeyavijayan
• 通讯作者: Rajendran, Jeyavijayan

Keynote: A Disquisition on Logic Locking

• DOI: 10.1109/tcad.2019.2944586
• 发表时间: 2020-10-01
• 期刊: IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS
• 影响因子: 2.9
• 作者: Chakraborty, Abhishek;Jayasankaran, Nithyashankari Gummidipoondi;Zuzak, Michael
• 通讯作者: Zuzak, Michael

Removal Attacks on Logic Locking and Camouflaging Techniques

• DOI: 10.1109/tetc.2017.2740364
• 发表时间: 2020-04
• 期刊: IEEE Transactions on Emerging Topics in Computing
• 影响因子: 5.9
• 作者: Muhammad Yasin;Bodhisatwa Mazumdar;O. Sinanoglu;Jeyavijayan Rajendran