SHF:Small: OSCARS: Optimizing Self-Configurable Analog ICs for Reliability and Security
SHF:Small: OSCARS: Optimizing Self-Configurable Analog ICs for Reliability and Security
批准号:
1815583
负责人:
Jeyavijayan Rajendran
金额:
$40.0万
依托单位国家:
美国
项目类别:
Standard Grant
财政年份:
2018
资助国家:
美国
项目状态:
已结题
起止时间:
2018-10-01 至 2022-09-30
中文摘要
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英文摘要
The production of computer chips, specifically analog designs, has largely moved offshore in recent years, reducing design complexity and fabrication cost, because the foundries and the manufacturing process have become expensive. Such chips suffer from two problems: imprecise manufacturing of devices at physical limits and attacks from the untrusted foundry. This project develops solutions that can solve both the problems at once. The project also will engage with and teach the next generation of cybersecurity experts using puzzle-, challenge-, and competition-based educational and outreach activities at the high-school, undergraduate, and graduate levels.The goal of this research is to develop a versatile analog IC design platform that can achieve simultaneous resiliency attacks from the untrusted foundry and improve performance in the presence of imprecise manufacturing. The main approach is built-in self-configuration enabled by efficient circuit implementation of power-on optimization, which is enhanced by logic locking, and systematic design-time optimization. The approach entails identifying the optimal tuning values to make the analog design perform as desired; these tuning knob values are kept as a secret to prevent attacks.This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.
期刊论文(5)
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科研奖励(0)
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DOI:
10.1109/tcsi.2018.2805641
发表时间:
2018-10-01
期刊:
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS
影响因子:
5.1
作者:
[Lee, Sanghoon, Shi, Congyin, Sanchez-Sinencio, Edgar]
通讯作者:
Sanchez-Sinencio, Edgar
Towards Provably-Secure Analog and Mixed-Signal Locking Against Overproduction
迈向可证明安全的模拟和混合信号锁定,防止生产过剩
DOI:
10.1109/tetc.2020.3025561
发表时间:
2020
期刊:
IEEE Transactions on Emerging Topics in Computing
影响因子:
5.9
作者:
[GummidipoondiJayasankaran, Nithyashankari, Sanabria Borbon, Adriana, Sanchez Sinencio, Edgar, Hu, Jiang, Rajendran, Jeyavijayan]
通讯作者:
Rajendran, Jeyavijayan
Breaking Analog Locking Techniques
突破模拟锁定技术
DOI:
10.1109/tvlsi.2020.3007159
发表时间:
2020
期刊:
IEEE Transactions on Very Large Scale Integration (VLSI
影响因子:
--
作者:
[Jayasankaran, Nithyashankari Gummidipoondi, Sanabria-Borbon, Adriana, Abuellil, Amr, Sanchez-Sinencio, Edgar, Hu, Jiang, Rajendran, Jeyavijayan]
通讯作者:
Rajendran, Jeyavijayan
DOI:
10.1109/itc44778.2020.9325209
发表时间:
2020-11
期刊:
2020 IEEE International Test Conference (ITC)
影响因子:
--
作者:
[Adriana C. Sanabria-Borbón;Nithyashankari Gummidipoondi Jayasankaran;S. Y. Lee;E. Sánchez-Sinencio;Jiang Hu;Jeyavijayan Rajendran]
通讯作者:
Adriana C. Sanabria-Borbón;Nithyashankari Gummidipoondi Jayasankaran;S. Y. Lee;E. Sánchez-Sinencio;Jiang Hu;Jeyavijayan Rajendran
DOI:
--
发表时间:
2019
期刊:
ACM/IEEE Asia and South Pacific Design Automation Conference
影响因子:
--
作者:
[Xu, W., Feng, L., Rajendran, J., Hu, J.]
通讯作者:
Hu, J.
Collaborative Research: EAGER: SaTC-EDU: Dynamic Adaptive Machine Learning for Teaching Hardware Security (DYNAMITES)
-
批准号:2039610
-
项目类别:Standard Grant
-
资助金额:$15.0万
-
财政年份:2020
-
负责人:Jeyavijayan Rajendran
-
依托单位:
EAGER: Collaborative: Secure and Trustworthy Cyberphysical Microfluidic Systems
-
批准号:1833623
-
项目类别:Standard Grant
-
资助金额:$7.0万
-
财政年份:2018
-
负责人:Jeyavijayan Rajendran
-
依托单位:
CAREER: Towards Provably-Secure Design of Integrated Circuits
-
批准号:1652842
-
项目类别:Continuing Grant
-
资助金额:$50.0万
-
财政年份:2017
-
负责人:Jeyavijayan Rajendran
-
依托单位:
STARSS: Small: Collaborative: Physical Design for Secure Split Manufacturing of ICs
-
批准号:1822840
-
项目类别:Standard Grant
-
资助金额:$9.59万
-
财政年份:2017
-
负责人:Jeyavijayan Rajendran
-
依托单位:
CAREER: Towards Provably-Secure Design of Integrated Circuits
-
批准号:1822848
-
项目类别:Continuing Grant
-
资助金额:$48.09万
-
财政年份:2017
-
负责人:Jeyavijayan Rajendran
-
依托单位:
STARSS: Small: Collaborative: Physical Design for Secure Split Manufacturing of ICs
-
批准号:1618797
-
项目类别:Standard Grant
-
资助金额:$15.33万
-
财政年份:2016
-
负责人:Jeyavijayan Rajendran
-
依托单位:
国内基金
海外基金
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