SHF:Small: OSCARS: Optimizing Self-Configurable Analog ICs for Reliability and Security

SHF:Small：OSCARS：优化自配置模拟 IC 以实现可靠性和安全性

• 批准号: 1815583
• 负责人: Jeyavijayan Rajendran
• 金额: $ 40万
• 依托单位: Texas A&M Engineering Experiment Station
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2018
• 资助国家: 美国
• 起止时间: 2018-10-01 至 2022-09-30
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=1815583&HistoricalAwards=false
• 关键词: SHF; Small; OSCARS; Optimizing; Self

The production of computer chips, specifically analog designs, has largely moved offshore in recent years, reducing design complexity and fabrication cost, because the foundries and the manufacturing process have become expensive. Such chips suffer from two problems: imprecise manufacturing of devices at physical limits and attacks from the untrusted foundry. This project develops solutions that can solve both the problems at once. The project also will engage with and teach the next generation of cybersecurity experts using puzzle-, challenge-, and competition-based educational and outreach activities at the high-school, undergraduate, and graduate levels.The goal of this research is to develop a versatile analog IC design platform that can achieve simultaneous resiliency attacks from the untrusted foundry and improve performance in the presence of imprecise manufacturing. The main approach is built-in self-configuration enabled by efficient circuit implementation of power-on optimization, which is enhanced by logic locking, and systematic design-time optimization. The approach entails identifying the optimal tuning values to make the analog design perform as desired; these tuning knob values are kept as a secret to prevent attacks.This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.

近年来，计算机芯片的生产，特别是模拟设计，已经在很大程度上转移到了海外，降低了设计复杂性和制造成本，因为代工厂和制造工艺变得昂贵。这种芯片面临两个问题：在物理限制下设备的不精确制造以及来自不可信代工厂的攻击。该项目开发的解决方案可以同时解决这两个问题。该项目还将在高中、本科和研究生阶段通过益智、挑战和竞赛等教育和推广活动，与下一代网络安全专家进行接触和教学。该研究的目标是开发一个多功能模拟IC设计平台，该平台可以同时实现来自不可信代工厂的弹性攻击，并在不精确制造的情况下提高性能。 主要的方法是内置的自我配置，使有效的电路实现的上电优化，这是增强逻辑锁定，和系统的设计时优化。该方法需要确定最佳调谐值，以使模拟设计按预期运行;这些调谐旋钮值被保密，以防止攻击。该奖项反映了NSF的法定使命，并通过使用基金会的知识价值和更广泛的影响审查标准进行评估，被认为值得支持。

项目成果

A Built-In Self-Test and In Situ Analog Circuit Optimization Platform

• DOI: 10.1109/tcsi.2018.2805641
• 发表时间: 2018-10-01
• 期刊: IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS
• 影响因子: 5.1
• 作者: Lee, Sanghoon;Shi, Congyin;Sanchez-Sinencio, Edgar
• 通讯作者: Sanchez-Sinencio, Edgar

Towards Provably-Secure Analog and Mixed-Signal Locking Against Overproduction

迈向可证明安全的模拟和混合信号锁定，防止生产过剩

• DOI: 10.1109/tetc.2020.3025561
• 发表时间: 2020
• 期刊: IEEE Transactions on Emerging Topics in Computing
• 影响因子: 5.9
• 作者: GummidipoondiJayasankaran, Nithyashankari;Sanabria Borbon, Adriana;Sanchez Sinencio, Edgar;Hu, Jiang;Rajendran, Jeyavijayan
• 通讯作者: Rajendran, Jeyavijayan

Breaking Analog Locking Techniques

突破模拟锁定技术

• DOI: 10.1109/tvlsi.2020.3007159
• 发表时间: 2020
• 期刊: IEEE Transactions on Very Large Scale Integration (VLSI
• 作者: Jayasankaran, Nithyashankari Gummidipoondi;Sanabria-Borbon, Adriana;Abuellil, Amr;Sanchez-Sinencio, Edgar;Hu, Jiang;Rajendran, Jeyavijayan
• 通讯作者: Rajendran, Jeyavijayan

Schmitt Trigger-Based Key Provisioning for Locking Analog/RF Integrated Circuits

• DOI: 10.1109/itc44778.2020.9325209
• 发表时间: 2020-11
• 期刊: 2020 IEEE International Test Conference (ITC)
• 作者: Adriana C. Sanabria-Borbón;Nithyashankari Gummidipoondi Jayasankaran;S. Y. Lee;E. Sánchez-Sinencio;Jiang Hu;Jeyavijayan Rajendran

Layout Recognition Attacks on Split Manufacturing

分割制造的布局识别攻击

• 发表时间: 2019
• 期刊: ACM/IEEE Asia and South Pacific Design Automation Conference
• 作者: Xu, W.;Feng, L.;Rajendran, J.;Hu, J.
• 通讯作者: Hu, J.