Collaborative Research: Defects Driven Reliability Modeling and Stress Burn-in Optimization in Nanoelectronics Manufacturing

成品率和可靠性是决定纳米电子制造成功的关键因素。传统上，它们是根据不同的信息来源单独评估的。成品率通常基于过程控制数据（诸如制造缺陷的测量）来估计;而可靠性预测通常依赖于从可靠性测试获得的寿命数据。在产品生命周期的早期阶段，当数据有限时，很难实施下线可靠性评估方法。如果成功的话，这项研究将使一个统一的框架，管理产量，可靠性和应力老化在纳米电子制造使用过程控制数据。此外，与此奖项相关的综合研究和教育计划将为来自代表性不足和贫困的阿巴拉契亚俄亥俄州地区的学生提供跨学科教育和研究机会，并通过K-12外展活动促进STEM教育。该奖项的重点是通过缺陷的时空建模的纳米电子产品的产量和可靠性。缺陷的空间建模和时间建模分别是指当器件经受应力时，缺陷的空间分布的建模和缺陷随时间的增长的建模。一个多学科的团队组成的两个PI与纳米电子制造和可靠性工程的专业知识，分别形成。将进行系统的加速破坏性降解试验，然后进行详细的失效物理分析，以探索失效机制，并推导出基于物理的随机缺陷增长模型。新的成品率模型将建立在缺陷尺寸分布和缺陷空间分布知识的基础上。基于缺陷增长机理和模型，提出了新的可靠性模型。可靠性模型将导致新的老化程序。通过基于等离子体的蚀刻工艺制备的宽度低于100纳米的超窄铜互连线将用作该方法的测试平台。

Yield and reliability are critical factors in determining the success of nanoelectronics manufacturing. They are traditionally evaluated separately based on different sources of information. Yield is generally estimated based on process control data such as measurements of manufacturing defects; while reliability prediction generally relies on lifetime data obtained from reliability tests. It is difficult to implement an end-of-line reliability assessment approach at early stages of a product's life cycle when data are limited. If successful, this research will enable a unified framework for managing yield, reliability, and stress burn-in in nanoelectronics manufacturing using process-control data. In addition, the integrated research and education plan associated with this award will provide interdisciplinary education and research opportunities for students from the underrepresented and impoverished Appalachian Ohio area and promote STEM education through K-12 outreach activities. This award focuses on yield and reliability of nanoelectronics products via spatiotemporal modeling of defects. The spatial modeling and temporal modeling of defects refer to modeling of the spatial distribution of defects and modeling of the growth of defects with time when devices are subject to stresses, respectively. A multidisciplinary team consisting of two PIs with expertise in nanoelectronics manufacturing and reliability engineering, respectively, is formed. Systematic accelerated destructive degradation tests followed by detailed physics-of-failure analysis will be conducted to explore failure mechanisms and to derive physics-based random defect-growth models. New yield models will be built based on the knowledge of defect size distribution and spatial distribution of defects. New reliability models will be suggested based on the defect-growth mechanisms and models. The reliability models will lead to new burn-in procedures. Ultra-narrow copper interconnect lines with sub 100 nanometers width prepared from a plasma-based etch process will be used as the testbed for the methodology.