Collaborative Research: An Effective and Efficient Low-Cost Alternate to Cell Aware Test Generation for Cell Internal Defects

协作研究：针对电池内部缺陷的电池感知测试生成有效且高效的低成本替代方案

• 批准号: 2331002
• 负责人: Abhijit Chatterjee
• 金额: $ 30万
• 依托单位: Georgia Tech Research Corporation
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2023
• 资助国家: 美国
• 起止时间: 2023-10-01 至 2026-09-30
• 项目状态: 未结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=2331002&HistoricalAwards=false
• 关键词: Collaborative; Research; Effective; Efficient; Low

Society’s growing reliance on intelligent electronic systems risks significant disruption and loss from integrated circuit failure. Mitigating this threat requires building electronic systems that have been extensively tested to ensure that they are fully functional and defect-free. Modern integrated circuits contain billions of transistors that makes a complete exhaustive test of circuit functionality impractical and infeasible. Such tests are generated in practice, by considering the impact of likely manufacturing defects such as shorts and opens at various circuit locations, and developing a set of input test patterns whose correct binary output is altered by the existence of any targeted fault, identifying a bad integrated circuit. However, it is not practical to model and target all possible malfunctions in a large circuit, especially those that employ deeply scaled technologies, low supply voltages and high clock speeds. As a consequence, some faulty circuits inevitably escape post-manufacture testing because of incomplete test coverage and cause integrated circuit failure when deployed in operation. The goal of this research is to develop better and significantly more cost-effective test methods for state-of-the-art integrated circuits that can significantly impact the affordability and reliability of future computing systems that are increasingly pervasive in day-to-day societal applications and critical for national defense. The project will also help train new students in this strategic area, consistent with recent priorities for US leadership in semiconductor manufacturing. Traditional test methods for integrated circuits generate test inputs that explicitly detect faulty behavior only at the terminals of the standard cell building blocks and the interconnections between these cells. It is now widely known that detection of defective devices can be enhanced by considering defects within the cell circuitry as well. To do this, currently, faults are injected one at a time at likely defect locations in the cell layout, followed by exhaustive circuit simulation of all possible input patterns to obtain cell level tests. The generated tests are then delivered to cells embedded in logic circuitry using circuit-level test generation algorithms. This has major drawbacks. First, it is expensive to characterize the full range of resistive defects at every possible location in large cells using exhaustive circuit simulation. In practice, only ideal shorts and opens are simulated, leading to test escapes. Second, this does not consider the significant impact of a timing delay in one cell on the delays of other interconnected cells. Third, existing test generation techniques such as cell aware test, can increase test size and application time by greater than fivefold. To address these issues, this project seeks to develop a new testing methodology that avoids exhaustive simulation, but instead uses analytical reasoning to generate tests for cell internal defects. Algorithms based on this analytic approach can generate compact tests that cover defects spanning large resistance ranges without the need for repeated simulations. Additionally, the delay impact of a single defect that affects multiple cells can also be effectively captured, minimizing the escape of timing faults.This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.

社会对智能电子系统的日益依赖有可能导致集成电路故障造成重大破坏和损失。要缓解这一威胁，需要建立经过广泛测试的电子系统，以确保它们功能齐全、没有缺陷。现代集成电路包含数十亿个晶体管，这使得对电路功能的全面测试变得不切实际和不可行。在实践中，通过考虑可能的制造缺陷的影响，例如在各个电路位置处的短路和开路，并开发其正确的二进制输出因任何目标故障的存在而改变的一组输入测试图案，来产生这样的测试，以识别不良集成电路。然而，对大型电路中所有可能的故障进行建模和定位是不切实际的，尤其是那些采用深度扩展技术、低电源电压和高时钟速度的电路。因此，一些有故障的电路由于测试覆盖不完整而不可避免地逃脱了制造后的测试，并在运行时导致集成电路故障。这项研究的目标是为最先进的集成电路开发更好、更具成本效益的测试方法，这些方法可以显著影响未来计算系统的可负担性和可靠性，这些计算系统在日常社会应用中日益普遍，对国防至关重要。该项目还将帮助培训这一战略领域的新学生，这与美国在半导体制造领域的领导地位最近的优先事项一致。用于集成电路的传统测试方法生成测试输入，该测试输入仅在标准单元构建块的端子和这些单元之间的互连处显式地检测故障行为。现在众所周知，也可以通过考虑单元电路内的缺陷来增强对缺陷器件的检测。为此，目前，在单元布局中的可能缺陷位置一次注入一个故障，然后对所有可能的输入模式进行详尽的电路模拟，以获得单元级测试。然后使用电路级测试生成算法将生成的测试递送到嵌入逻辑电路中的单元。这有很大的缺点。首先，使用穷举电路模拟来表征大单元中每个可能位置的全部电阻缺陷是昂贵的。在实践中，只有理想的空头和开盘被模拟，从而导致测试逃逸。其次，这没有考虑一个信元中的定时延迟对其他互连信元的延迟的显著影响。第三，现有的测试生成技术，如单元感知测试，可以将测试大小和应用时间增加五倍以上。为了解决这些问题，该项目寻求开发一种新的测试方法，该方法避免穷尽的模拟，而是使用分析推理来生成单元内部缺陷的测试。基于这种分析方法的算法可以生成覆盖大电阻范围的缺陷的紧凑测试，而不需要重复模拟。此外，还可以有效地捕获影响多个单元的单个缺陷的延迟影响，最大限度地减少定时故障的逃逸。这一裁决反映了NSF的法定使命，并通过使用基金会的智力优势和更广泛的影响审查标准进行评估，被认为值得支持。