CNS: CSR: Small: Exploiting 3D Memory for Energy-Efficient Memory-Driven Computing

CNS：CSR：小型：利用 3D 内存实现节能内存驱动计算

• 批准号: 1643351
• 负责人: Viktor Prasanna
• 金额: $ 49.78万
• 依托单位: University of Southern California
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2016
• 资助国家: 美国
• 起止时间: 2016-10-01 至 2020-09-30
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=1643351&HistoricalAwards=false
• 关键词: CNS; CSR; Small; Exploiting; 3D

Semiconductor technology is facing fundamental physical limits creating an increased demand for acceleration of data-intensive applications on architectures that bring memory much closer to reconfigurable compute logic. Three dimensional integrated circuits (3DIC) appear to be the most prominent technology towards memory-driven computing by enabling large amounts of memory stacked in layers to be accessed by a logic unit using high bandwidth vertical interconnects. Software-defined technologies can provide the framework for harnessing the potential breakthrough performance of 3D and other advanced memory technologies in a holistic but dynamic manner, while at the same time hiding their internal complexity. This project focuses on developing a novel software paradigm to perform algorithmic exploration of memory-driven computing on new memory architectures and facilitate the development of massively parallel algorithms for memory-unconstrained computing with the potential for breakthrough performance levels. The project will develop Software-Defined 3D Memory (SD3DM) as a transformative layer for memory-driven computing that will not simply virtualize 3D memory but will holistically address the oncoming reality of massive on-chip 3D Memory for accelerating data-intensive applications while jointly optimizing energy consumption. Memory access optimizations will be developed at the algorithm level to meet application performance objectives of throughput, latency, and energy efficiency. Specifically, the optimizations will be designed to fully exploit the characteristics of target architectures by (i) carefully defining application-specific dynamic data layouts, (ii) developing application-specific memory controllers for runtime support, and (iii) designing novel in-memory data permutation mechanisms to accelerate inter-stage communication. Integer Linear Programming (ILP) and Stochastic Programming (SP) based dynamic data layouts that exploit the interlayer pipelining and parallel vault access features of 3D memory for throughput and energy-optimal mapping of data to different memory components will be developed. Data layout algorithms will be developed in in conjunction with application-specific memory controllers to provide maximum pipeline execution efficiency for any given application. The proposed optimizations will be demonstrated on widely used signal processing and machine learning algorithms with diverse data access and logic use requirements. Successful completion of this project will directly lead to a significant increase in the size of signal processing and machine learning problems that can be solved on emerging 3DIC platforms at speeds that were not possible before. The developed work will potentially influence multiple application domains. The investigators will encourage the participation by women, minorities, and under-represented groups in the project through USC's Minority Opportunities in Research (MORE) Programs.

半导体技术正面临着基本的物理限制，这使得对加速架构上的数据密集型应用的需求增加，这些架构使存储器更接近可重构计算逻辑。三维集成电路（3DIC）似乎是朝向存储器驱动的计算的最突出的技术，其通过使得能够由使用高带宽垂直互连的逻辑单元访问堆叠在层中的大量存储器。软件定义技术可以提供一个框架，以整体但动态的方式利用3D和其他先进存储技术的潜在突破性性能，同时隐藏其内部复杂性。该项目的重点是开发一种新的软件范例，以在新的内存架构上进行内存驱动计算的算法探索，并促进开发具有突破性能水平潜力的内存无约束计算的大规模并行算法。 该项目将开发软件定义的3D内存（SD3DM）作为内存驱动计算的变革层，不仅将3D内存虚拟化，还将全面解决即将到来的大规模片上3D内存的现实，以加速数据密集型应用，同时共同优化能耗。将在算法级别开发内存访问优化，以满足吞吐量、延迟和能效等应用程序性能目标。具体而言，优化将被设计为通过以下方式充分利用目标架构的特性：（i）仔细定义特定于应用程序的动态数据布局，（ii）开发用于运行时支持的特定于应用程序的内存控制器，以及（iii）设计新颖的内存数据置换机制以加速级间通信。将开发基于线性规划（ILP）和随机规划（SP）的动态数据布局，这些动态数据布局利用3D存储器的层间流水线和并行存储库访问功能，以实现数据到不同存储器组件的吞吐量和能量优化映射。数据布局算法将与特定应用程序的存储器控制器一起开发，为任何给定的应用程序提供最大的流水线执行效率。提出的优化将在广泛使用的信号处理和机器学习算法上进行演示，这些算法具有不同的数据访问和逻辑使用要求。该项目的成功完成将直接导致信号处理和机器学习问题的规模显著增加，这些问题可以在新兴的3DIC平台上以以前不可能的速度解决。开发的工作将潜在地影响多个应用领域。调查人员将鼓励妇女，少数民族和代表性不足的群体通过南加州大学的少数民族研究机会（更多）计划参与该项目。

项目成果

QTAccel: A Generic FPGA based Design for Q-Table based Reinforcement Learning Accelerators

QTAccel：基于 Q-Table 的强化学习加速器的通用 FPGA 设计

• DOI: 10.1109/ipdpsw50202.2020.00024
• 发表时间: 2020
• 期刊: 2020 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW
• 作者: Meng, Yuan;Kuppannagari, Sanmukh;Rajat, Rachit;Srivastava, Ajitesh;Kannan, Rajgopal;Prasanna, Viktor
• 通讯作者: Prasanna, Viktor

Throughput-Optimized Frequency Domain CNN with Fixed-Point Quantization on FPGA

FPGA 上具有定点量化的吞吐量优化频域 CNN

• DOI: 10.1109/reconfig.2018.8641716
• 发表时间: 2018
• 期刊: 2018 International Conference on ReConFigurable Computing and FPGAs (ReConFig
• 作者: Sun, Weiyi;Zeng, Hanqing;Yang, Yi-hua Edward;Prasanna, Viktor
• 通讯作者: Prasanna, Viktor

Accelerating Large Scale GCN Inference on FPGA

• DOI: 10.1109/fccm48280.2020.00074
• 发表时间: 2020-05
• 期刊: 2020 IEEE 28th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM)
• 作者: Bingyi Zhang;Hanqing Zeng;V. Prasanna

FASTCF: FPGA-based Accelerator for STochastic-Gradient-Descent-based Collaborative Filtering

• DOI: 10.1145/3174243.3174252
• 发表时间: 2018-02
• 期刊: Proceedings of the 2018 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays
• 作者: Shijie Zhou;R. Kannan;Yu Min;V. Prasanna

A Flexible Design Automation Tool for Accelerating Quantized Spectral CNNs

• DOI: 10.1109/fpl.2019.00031
• 发表时间: 2019-09
• 期刊: 2019 29th International Conference on Field Programmable Logic and Applications (FPL)
• 作者: Rachit Rajat;Hanqing Zeng;V. Prasanna