CNS: CSR: Small: Exploiting 3D Memory for Energy-Efficient Memory-Driven Computing

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Semiconductor technology is facing fundamental physical limits creating an increased demand for acceleration of data-intensive applications on architectures that bring memory much closer to reconfigurable compute logic. Three dimensional integrated circuits (3DIC) appear to be the most prominent technology towards memory-driven computing by enabling large amounts of memory stacked in layers to be accessed by a logic unit using high bandwidth vertical interconnects. Software-defined technologies can provide the framework for harnessing the potential breakthrough performance of 3D and other advanced memory technologies in a holistic but dynamic manner, while at the same time hiding their internal complexity. This project focuses on developing a novel software paradigm to perform algorithmic exploration of memory-driven computing on new memory architectures and facilitate the development of massively parallel algorithms for memory-unconstrained computing with the potential for breakthrough performance levels. The project will develop Software-Defined 3D Memory (SD3DM) as a transformative layer for memory-driven computing that will not simply virtualize 3D memory but will holistically address the oncoming reality of massive on-chip 3D Memory for accelerating data-intensive applications while jointly optimizing energy consumption. Memory access optimizations will be developed at the algorithm level to meet application performance objectives of throughput, latency, and energy efficiency. Specifically, the optimizations will be designed to fully exploit the characteristics of target architectures by (i) carefully defining application-specific dynamic data layouts, (ii) developing application-specific memory controllers for runtime support, and (iii) designing novel in-memory data permutation mechanisms to accelerate inter-stage communication. Integer Linear Programming (ILP) and Stochastic Programming (SP) based dynamic data layouts that exploit the interlayer pipelining and parallel vault access features of 3D memory for throughput and energy-optimal mapping of data to different memory components will be developed. Data layout algorithms will be developed in in conjunction with application-specific memory controllers to provide maximum pipeline execution efficiency for any given application. The proposed optimizations will be demonstrated on widely used signal processing and machine learning algorithms with diverse data access and logic use requirements. Successful completion of this project will directly lead to a significant increase in the size of signal processing and machine learning problems that can be solved on emerging 3DIC platforms at speeds that were not possible before. The developed work will potentially influence multiple application domains. The investigators will encourage the participation by women, minorities, and under-represented groups in the project through USC's Minority Opportunities in Research (MORE) Programs.