Development of novel system and component architectures for future multichannel 100 GBit/s communication systems (M-SPARS)

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Ultra high-speed wireless communication can be achieved by means of extremely high carrier frequencies. Antenna configurations with high directivity are typically used in this context to reach an acceptable signal-to-noise ratio. Thus, single channel systems are inflexible given the need to correctly align the transmitting and receiving antennas. Multi-antenna systems, e.g. MIMO systems, are needed to address nodes, regardless of direction. Transceivers with an extremely high carrier frequency are nowadays based on semiconductor technologies that operate close to the maximum transit frequency that is available today. Given that, classical homodyne transceivers therefore need amplifier chains comprising several stages as well as elaborate quadrature modulators and demodulators; hence, the overall prospect w.r.t. chip surface-area requirements and power consumption for the classical homodyne approach to build multiple-antenna systems is extremely challenging. The aim of this project is to research, innovative build options for 100 Gbit/s multi-channel communication systems based on an entirely new type of transceiver architecture with drastically reduced circuit complexity. The project is a continuation of the first phase of the SPP 1655 project SPARS, which verified that complex low-noise- and power-amplifier chains can be replaced by the single-stage switched injection-locked oscillator (SILO) and by regeneration with positive feedback, and that 16 QAM modulated signals can be generated at a much lower power level and with lower circuit complexity. The transceiver structure will be simplified and improved and compact multi-channel architectures that are optimally integrable will be designed in the next project phase. The quadrature channel, and thus a complete signal path, will be removed from the receiver, and thereby also the DC-, phase- and gain offset problems are effectively reduced. This is achieved with an IF of 25 GHz, produced with a novel differential demodulation section with two synchronously modulated SILOs with offset frequency and a 100 GS/s A/D converter with 40 GHz analog bandwidth. The IF at 1/4 the sampling rate can be efficiently demodulated and the heterodyne baseband can be seamlessly extended to multiple channels. Compact BPSK modulators are deployed in the transmitter. Amplitude modulation is implemented by a pulse width modulation of the SILO studied in project phase 1. The SILO architecture is now upgraded to synchronously modulated SILO arrays for the first time. There is also no need for IQ mixers in the transmitter in the new concept. A systems model will be developed to provide a theoretical basis for this new and drastically simplified transceiver architecture and to investigate disturbances like phase jitter and frequency drift in the SILO arrays. Complete transmitter and receiver frontends for two channels with a center frequency of 180 GHz will be built to demonstrate and verify the concepts.