Electronic Analog Multiplexer for High-Speed Communication Systems (ELAMUR)

全球传输网络中数据业务量的不间断增长需要增加带宽，特别是在光网络中。由于成本随光通道数量的增加而增加，使得每个光通道的数据速率最大化是有益的，这就要求增加单个通道的信号带宽，这种增长的带宽对发射机和接收机的电子学提出了更高的要求。在发送端，这尤其适用于电子数模转换器(DAC)。在过去的几年里，65到28 nm工艺的CMOSDAC已经满足了发射机日益增长的带宽需求。它们提供56到92 GS/S的转换速率；然而，在过去的几年中，很明显，最大转换速率几乎不会超过130GS/S。而且，即使在最新的CMOS技术(例如7 nm FIN-FET)中，输出带宽也几乎不会达到远远超过40 GHz的值。因此，迫切需要新的电路概念来进一步增加每通道的电带宽。为此，需要几个DAC输出信号与集成电路的纯电复用。符合条件的技术是频分复用和模拟时分复用。频分多路复用需要集总混频器和高Q模拟滤波器，这些都不能很好地适应高集成度。只有模拟时分复用才能实现单个紧凑的单片集成芯片，该芯片将多个DAC输出信号组合成单个信号。申请者已经在2017年展示了波特率高达112 GBD的模拟2对1多路复用器(AMUX)。在此项目中，将研究和演示至少四个输入提供高达200 GBD波特率和超过100 GHz信号带宽的模拟多路复用器。应研究不同的基本电路拓扑，以找到关于带宽和信号质量的最合适的电路配置。电路应转换为版图，并在IHP的双极技术SG13G2中制造。应识别电路内部线性和非线性失真的来源，并将其嵌入行为模型。应确定、研究和实施适用于信号预失真的线性和非线性方法。使用商用四通道信号发生器、演示IC和所设计的信号预失真，可以演示带宽高达100 GHz、符号率高达200GBD的高质量电信号。此外，宽带信号将在光链路上传输。

The uninterrupted growth in data traffic in the global transmission networks requires increased bandwidths, especially in the optical networks. Due to the cost scaling with the number of optical channels, it is beneficial to maximize the data rate per optical channel, which requires an increase of the signal bandwidth for the single channel.This growing bandwidth imposes higher requirements on the electronics of the transmitter and the receiver. On the transmitter side, this applies in particular to the electronic digital-to-analog converters (DAC). The growing demand for bandwidth in transmitters has been satisfied with CMOS DACs in 65 to 28 nm technology in the past years. They provide conversion rates of 56 to 92 GS/s; however, it has been become apparent in the last years that the maximum conversion rate will hardly increase beyond 130 GS/s. Moreover, the output bandwidth will barely reach values far beyond 40 GHz, even in the latest CMOS technologies (e.g. 7 nm Fin-FET).Therefore, new circuit concepts are urgently needed to further increase the electrical bandwidth per channel. For this purpose, a pure electrical multiplex of several DAC output signals with an integrated circuit is desirable. The eligible techniques are frequency division multiplex and analog time division multiplex. Frequency division multiplex requires lumped mixers and high-Q analog filters, which are not well suited for a high level in integration. Solely, analog time division multiplex enables a single compact monolithic integrated chip, which combines several DAC output signals to a single signal. The applicants have already demonstrated an analog 2-to-1 multiplexer (AMUX) for baud rates up to 112 GBd in 2017.In this project, analog multiplexers with at least four inputs offering baud rates up to 200 GBd and signal bandwidths exceeding 100 GHz shall be researched and demonstrated. Different basic circuit topologies shall be investigated to find the best-suited circuit configuration regarding bandwidth and signal quality. The circuit shall be transferred into a layout and manufactured in the bipolar technology SG13G2 of IHP. The sources of linear and nonlinear distortion inside the circuit shall be identified and embedded into a behavioral model. Appropriate linear and nonlinear methods for signal pre-distortion shall be identified, investigated and implemented. With a commercial four-channel signal generator, the demonstrator IC and the designed signal pre-distortion, electrical signals of high quality with bandwidth up to 100 GHz and symbol rate up to 200 GBd shall be demonstrated. Furthermore, the broadband signal will be transmitted over an optical link.