Electronic Analog Multiplexer for High-Speed Communication Systems (ELAMUR)

全球传输网络中数据流量的不间断增长需要增加带宽，特别是在光网络中。由于成本随光信道数量的增加而增加，因此最大化每个光信道的数据速率是有益的，这需要增加单个信道的信号带宽，这种增加的带宽对发射机和接收机的电子器件提出了更高的要求。在发射机侧，这尤其适用于电子数模转换器（DAC）。过去几年，采用65至28 nm工艺的CMOS DAC满足了发射机对带宽不断增长的需求。它们提供56至92 GS/s的转换率;然而，过去几年中已明显看出，最高转换率几乎不会超过130 GS/s。此外，即使在最新的CMOS技术（例如7 nm Fin-FET）中，输出带宽也几乎不会超过40 GHz。因此，迫切需要新的电路概念来进一步增加每个通道的电带宽。为此目的，需要用集成电路对几个DAC输出信号进行纯电复用。适合的技术有频分复用和模拟时分复用。频分多路复用需要集总混频器和高Q模拟滤波器，这不太适合高集成度。只有模拟时分多路复用才能实现单个紧凑型单片集成芯片，将多个DAC输出信号组合为单个信号。申请人已经在2017年演示了波特率高达112 GBd的模拟2比1多路复用器（AMUX）。在本项目中，应研究和演示具有至少四个输入的模拟多路复用器，其波特率高达200 GBd，信号带宽超过100 GHz。应研究不同的基本电路拓扑，以找到带宽和信号质量方面最适合的电路配置。电路应转换为布局，并采用IHP的双极技术SG 13 G2制造。应识别电路内部的线性和非线性失真源，并将其嵌入行为模型中。应确定、调查和实施信号预失真的适当线性和非线性方法。使用商用四通道信号发生器、演示器IC和设计的信号预失真器，可演示带宽高达100 GHz、符号速率高达200 GBd的高质量电信号。此外，宽带信号将通过光链路传输。

The uninterrupted growth in data traffic in the global transmission networks requires increased bandwidths, especially in the optical networks. Due to the cost scaling with the number of optical channels, it is beneficial to maximize the data rate per optical channel, which requires an increase of the signal bandwidth for the single channel.This growing bandwidth imposes higher requirements on the electronics of the transmitter and the receiver. On the transmitter side, this applies in particular to the electronic digital-to-analog converters (DAC). The growing demand for bandwidth in transmitters has been satisfied with CMOS DACs in 65 to 28 nm technology in the past years. They provide conversion rates of 56 to 92 GS/s; however, it has been become apparent in the last years that the maximum conversion rate will hardly increase beyond 130 GS/s. Moreover, the output bandwidth will barely reach values far beyond 40 GHz, even in the latest CMOS technologies (e.g. 7 nm Fin-FET).Therefore, new circuit concepts are urgently needed to further increase the electrical bandwidth per channel. For this purpose, a pure electrical multiplex of several DAC output signals with an integrated circuit is desirable. The eligible techniques are frequency division multiplex and analog time division multiplex. Frequency division multiplex requires lumped mixers and high-Q analog filters, which are not well suited for a high level in integration. Solely, analog time division multiplex enables a single compact monolithic integrated chip, which combines several DAC output signals to a single signal. The applicants have already demonstrated an analog 2-to-1 multiplexer (AMUX) for baud rates up to 112 GBd in 2017.In this project, analog multiplexers with at least four inputs offering baud rates up to 200 GBd and signal bandwidths exceeding 100 GHz shall be researched and demonstrated. Different basic circuit topologies shall be investigated to find the best-suited circuit configuration regarding bandwidth and signal quality. The circuit shall be transferred into a layout and manufactured in the bipolar technology SG13G2 of IHP. The sources of linear and nonlinear distortion inside the circuit shall be identified and embedded into a behavioral model. Appropriate linear and nonlinear methods for signal pre-distortion shall be identified, investigated and implemented. With a commercial four-channel signal generator, the demonstrator IC and the designed signal pre-distortion, electrical signals of high quality with bandwidth up to 100 GHz and symbol rate up to 200 GBd shall be demonstrated. Furthermore, the broadband signal will be transmitted over an optical link.