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Fastest Digital-to-Analog-Converter with low power consumption in FDSOI-CMOS Technology for Ultra-Broadband Data Transmission

采用 FDSOI-CMOS 技术的低功耗最快数模转换器，用于超宽带数据传输

基本信息

批准号：
276016065
负责人：
Professor Dr.-Ing. Manfred Berroth
金额：
--
依托单位：
Institut für Elektrische und Optische Nachrichtentechnik (INT)
依托单位国家：
德国
项目类别：
Research Grants
财政年份：
2015
资助国家：
德国
起止时间：
2014-12-31 至 2021-12-31
项目状态：
已结题

来源：
https://gepris.dfg.de/gepris/projekt/276016065?language=en
关键词：
Fastest Digital Analog Converter low

项目摘要

In the first project period of two years with the topic “Ultrafast digital-to-analog converters in FDSOI CMOS for ultra-broadband communication” new circuit topologies for ultrafast and high bandwidth digital-to-analog converters (DACs) in CMOS technology have been investigated. The research activities culminated in the design of a 128 GS/s 8 bit DAC demonstrator IC including a 256 kByte on-chip memory in a 28 nm FDSOI CMOS technology which has been assigned for tape-out.Concerning new topologies, a voltage-based 8 bit segmented DAC core with conversion rates up to 64 GS/s has to be mentioned at first. The DAC output consists of 15 unary output stages for the four MSBs and a binary weighted network for the four LSBs. One unary output stage consists of a CMOS inverter and a series resistance. The binary weighted part consists of four CMOS inverters and a four-stage R-2R network. The implemented DAC core shows the feasibility of ultrafast DAC cores in a voltage-based concept, and may replace traditional current-based approaches that need larger supply voltages. The low supply voltage of slightly above 1 V is the main advantage of this new architecture and is compatible with the core CMOS logic supply voltage. The power dissipation of the 64 GS/s core is only around 1,17 W. Another important innovative concept that is required for the realization of the 64 Gbit/s driver chains and the 32 GHz clock paths are CMOS inverter based driver chains with resistive negative feedback to increase the bandwidth. The second key component of the demonstrator IC is an analog multiplexer (AMUX) combining the output signals of the two 64 GS/s DAC cores by time interleaving to a single 128 GS/s output. Such a fast AMUX has been realized for the first time in CMOS technology within this project.In case of a successful demonstration of the 128 GS/s conversion rate, this IC would be the fastest monolithic electronic DAC to the best of the authors’ knowledge. Furthermore, the predicted output bandwidth of 32 GHz would be the highest one ever demonstrated in CMOS technology.The first aim of the project continuation is to start operation of the DAC and to characterize in detail the different parts of the IC and the output signal quality. As there are different linear and nonlinear effects in the implemented DAC chip which distort the output signal and reduce resolution, distortion compensation procedures shall be investigated and implemented to increase performance. Finally, different applications of the AWG module shall be demonstrated by applying these compensation methods. A broad spectrum of applications ranging from very broadband optical link signals to micro- and mm-wave signals, e.g. for mobile and data communication of the 5th generation (5G), will be demonstrated during this project.

在为期两年的第一个项目期内，主题为“用于超宽带通信的FDSOI CMOS超快数模转换器”，研究了用于CMOS技术的超快和高带宽数模转换器（DAC）的新电路拓扑。研究活动的最终成果是设计了一个128 GS/s的8位DAC演示IC，包括一个256 kByte的片上存储器，采用28 nm FDSOI CMOS技术，已被指定用于流片。关于新的拓扑结构，首先必须提到一个基于电压的8位分段DAC核心，转换速率高达64 GS/s。DAC输出由15个一元输出级（用于4个MSB）和一个二进制加权网络（用于4个LSB）组成。一元输出级由CMOS反相器和串联电阻组成。二进制加权部分由四个CMOS反相器和一个四级R-2 R网络组成。实现的DAC内核显示了基于电压的超快DAC内核的可行性，并可能取代传统的基于电流的方法，需要更大的电源电压。略高于1 V的低电源电压是这种新架构的主要优势，并且与核心CMOS逻辑电源电压兼容。64 GS/s内核的功耗仅为1.17 W左右。实现64 Gbit/s驱动器链和32 GHz时钟路径所需的另一个重要创新概念是基于CMOS反相器的驱动器链，该驱动器链具有电阻性负反馈以增加带宽。演示IC的第二个关键组件是模拟多路复用器（AMUX），它通过时间交错将两个64 GS/s DAC内核的输出信号组合为单个128 GS/s输出。在本项目中，这种快速的AMUX是第一次在CMOS工艺中实现，如果能成功实现128 GS/s的转换速率，则该IC将是目前最快的单片电子DAC。此外，预计32 GHz的输出带宽将是CMOS技术中有史以来最高的输出带宽。该项目继续的第一个目标是开始DAC的操作，并详细表征IC的不同部分和输出信号质量。由于在所实施的DAC芯片中存在不同的线性和非线性效应，这些效应会使输出信号失真并降低分辨率，因此应研究并实施失真补偿程序以提高性能。最后，通过应用这些补偿方法来演示AWG模块的不同应用。该项目将展示从超宽带光链路信号到微波和毫米波信号的广泛应用，例如第五代（5G）的移动的和数据通信。