CRII: SHF: WINGS -- Wireless Interconnects for Next-Generation Systems

低延迟、高能效和可重构的片上无线互连基础设施的发展有可能减少电子系统的碳足迹。该研究将与学院PI教授的超大规模集成电路和纳米电子器件设计研究生课程相结合。通过普渡大学的nano-HUB设施，本研究中生成的开源软件的传播有望通过服务于学生、研究人员和工程师的广泛社区而产生重大影响。此外，本研究中生成的软件将用于课堂项目和作业，为学生提供一个独特的机会来学习百亿亿级计算，而无需抽象设备物理的基础知识。本科学生将通过纽约大学工程学院的本科暑期研究项目获得建议。PI参与纽约大学国家技术女性中心项目将促进未被充分代表的少数民族参与研究项目。本研究的技术目标是通过利用石墨烯中的等离子体波来实现波导和纳米天线，在片上通信基础设施的设计和优化方面取得重大进展。通过结合不同的技术- CMOS电子和石墨烯等离子体-提出了一种新的异构架构，可以在10厘米范围内的几个计算元件之间实现太赫兹波段通信。该项目将开发一个基于分析模型的互连架构基准设计空间探索，涵盖实施方面（面积和能源）和网络级考虑（核心数量和网络架构）。总的来说，这项研究将通过改善异构计算环境中的通信瓶颈，推动扩展CMOS连接的全部潜力。

The development of low-latency, energy-efficient, and reconfigurable on-chip wireless interconnect infrastructure has the potential for reducing the carbon footprint of electronic systems. This research will be integrated with the graduate-level courses on design of VLSI and Nano-electronic devices to be taught by the PI at her institution. The dissemination of open-source software generated in this research via nano-HUB facilities at Purdue University is expected to provide significant impact by serving a broad community of students, researchers, and engineers. Further, the software generated in this research will be used for in-class projects and assignments providing students with a unique opportunity to learn about Exascale computing without abstracting the fundamentals of device physics. Undergraduate students will be advised through the undergraduate summer research program at NYU School of Engineering. Participation of the PI in National Center for Women in Technology program at NYU will facilitate involvement of underrepresented minorities in the research program. The technical objective of this research is to make major advances in the design and optimization of on-chip communications infrastructure by exploiting plasma waves in graphene to implement waveguides and nanoantennas. By marrying disparate technologies - CMOS electronics and graphene plasmonics - a new heterogeneous architecture is proposed to enable terahertz-band communication between several computing elements within a range of 10 cm. The project will develop an analytical model-based benchmarked design space exploration of the interconnect architecture covering implementation aspects (area and energy) and network-level consideration (number of cores and network architecture). Overall, this research will drive connectivity to the full potential of scaled CMOS by improving communication bottleneck in a heterogeneous computing environment.