CRII: SHF: WINGS -- Wireless Interconnects for Next-Generation Systems

低延迟、高能效和可重新配置的片上无线互连基础设施的开发有可能减少电子系统的碳足迹。这项研究将与她所在机构的PI教授的关于超大规模集成电路和纳米电子器件设计的研究生课程相结合。通过普渡大学的Nano-Hub设施传播这项研究中产生的开源软件，预计将通过服务于广泛的学生、研究人员和工程师社区而产生重大影响。此外，在这项研究中生成的软件将用于课堂项目和作业，为学生提供一个独特的机会，在不抽象设备物理基础的情况下学习亿级计算。本科生将通过纽约大学工程学院的本科生暑期研究项目获得建议。参与纽约大学国家妇女技术中心方案的PI将促进代表人数不足的少数群体参与研究方案。这项研究的技术目标是通过利用石墨烯中的等离子体波来实现波导和纳米天线，从而在片上通信基础设施的设计和优化方面取得重大进展。通过结合不同的技术--CMOS电子学和石墨烯等离子体--提出了一种新的异质体系结构，使几个计算元件之间能够在10厘米的范围内进行太赫兹波段通信。该项目将开发基于分析模型的互连架构基准设计空间探索，涵盖实施方面(面积和能源)和网络一级的考虑因素(核心数量和网络架构)。总体而言，这项研究将通过改善异质计算环境中的通信瓶颈来充分发挥可扩展CMOS的潜力。

The development of low-latency, energy-efficient, and reconfigurable on-chip wireless interconnect infrastructure has the potential for reducing the carbon footprint of electronic systems. This research will be integrated with the graduate-level courses on design of VLSI and Nano-electronic devices to be taught by the PI at her institution. The dissemination of open-source software generated in this research via nano-HUB facilities at Purdue University is expected to provide significant impact by serving a broad community of students, researchers, and engineers. Further, the software generated in this research will be used for in-class projects and assignments providing students with a unique opportunity to learn about Exascale computing without abstracting the fundamentals of device physics. Undergraduate students will be advised through the undergraduate summer research program at NYU School of Engineering. Participation of the PI in National Center for Women in Technology program at NYU will facilitate involvement of underrepresented minorities in the research program. The technical objective of this research is to make major advances in the design and optimization of on-chip communications infrastructure by exploiting plasma waves in graphene to implement waveguides and nanoantennas. By marrying disparate technologies - CMOS electronics and graphene plasmonics - a new heterogeneous architecture is proposed to enable terahertz-band communication between several computing elements within a range of 10 cm. The project will develop an analytical model-based benchmarked design space exploration of the interconnect architecture covering implementation aspects (area and energy) and network-level consideration (number of cores and network architecture). Overall, this research will drive connectivity to the full potential of scaled CMOS by improving communication bottleneck in a heterogeneous computing environment.