FuSe/Collaborative Research: Heterogeneous Integration in Power Electronics for High-Performance Computing (HIPE-HPC)

用于计算的能源占全球能源消耗的2%以上，其中很大一部分浪费在向微处理器供电的最后阶段。因此，提高效率和缩小尺寸(以克服空间限制)是下一代高性能计算电源交付解决方案的主要目标。这些要求开关和电感能够以较低的损耗支持较高的电压、电流和频率。硅(Si)互补金属氧化物半导体(CMOS)技术可以提供高水平的集成和控制，但Si CMOS开关具有较高的开关损耗。宽禁带半导体材料可以实现更好的开关，但它们不能很容易地与硅CMOS工艺集成。高性能的电力输送解决方案还要求紧凑型集成电感能够支持更高的功率、更高的小型化频率和更低的铁损。该未来半导体(FUSE)项目采用宽禁带半导体器件和片上铁氧体电感的共同设计和异质集成，采用CMOS技术和新的功率转换架构，以开发用于高性能计算的下一代集成功率传输系统。该项目将对用于高性能计算的高效后端集成电力输送系统的技术基础做出贡献，并提高美国在半导体制造领域的竞争力，从而产生重大的科学和社会影响。该项目还将加强对研究生和本科生在半导体、磁学、电力电子、集成电路、高性能计算等核心技术等基本主题上的教育。还计划实施一项广泛的劳动力发展计划，以吸引学生进入与该项目相关的领域，并教育已经在该行业工作的人，重点是代表性不足的群体。该项目的研究、教育和劳动力发展活动的结果评估将通过对定性和定量数据的内部和外部调查进行。用于高性能计算的电力电子3D异质集成将通过利用内插器实现，该内插器具有集成了新型旋转喷射沉积铁氧体的磁电感、先进的高压GaN开关、新型单级负载点功率转换器架构和集成的高压恒频移相控制电路。铁氧体的旋转喷射沉积使集成厚膜铁氧体薄膜在芯片上具有高相对磁导率~3000，该薄膜的水溶液具有易于定制的成分，可在~90℃的低温下用于硅、印刷电路板或其他集成电力电子基板上的集成电感和变压器。高压增强型GaN器件将利用3D雕塑场管理来实现记录功率优势系数。单级负载点转换架构可以在宽电压和功率范围内保持零电压和近零电流开关，并实现高功率密度和高而平坦的效率。功率转换架构、基于CMOS集成电路的控制、高性能GaN开关、集成磁性元件的插入器和磁性材料的联合设计将有助于实现用于高性能计算的紧凑和高效的集成后端负载点电力电子设备。此次融合合作设计将由一支拥有互补专业知识的合格团队进行，专业知识涵盖宽禁带半导体开关、磁性材料和集成磁性元件、CMOS控制电路和电源转换架构。这项活动还将产生利用电路模拟和多物理分析以及设计工具的新的联合设计方法。该奖项反映了NSF的法定使命，并通过使用基金会的智力优势和更广泛的影响审查标准进行评估，被认为值得支持。

The energy utilized for computing is more than 2 percent of global energy consumption, and a substantial fraction of it is wasted in the final stages of power delivery to microprocessors. Hence, efficiency improvement and size reduction (to overcome space limitations) are the main objectives for the next generation of power delivery solutions for high-performance computing. These require switches and inductors that can support higher voltages, currents, and frequencies with lower losses. Silicon (Si) complementary metal-oxide semiconductor (CMOS) technology can provide a high level of integration and control, but Si CMOS switches have higher switching losses. Wide-bandgap semiconductor materials enable better switches, but they cannot be easily integrated with the Si CMOS process. High-performance power delivery solutions also require compact integrated inductors that can support higher power, higher frequencies for miniaturization, and lower core losses. This Future of Semiconductors (FuSe) project uses co-designing and heterogeneous integration of wide-bandgap semiconductor devices and on-chip ferrite inductors with CMOS technology and a new power conversion architecture to develop next-generation integrated power delivery systems for high-performance computing. The project will have a significant scientific and societal impact by contributing to the technological foundations of highly efficient backside integrated power delivery systems for high-performance computing and enhancing US competitiveness in semiconductor manufacturing. The project will also strengthen the education of graduate and undergraduate students on essential topics of semiconductors, magnetics, power electronics, integrated circuits, high-performance computing, among other core technologies. An extensive workforce development program is also planned to attract students to the fields related to this project and to educate people already working in the industry with an emphasis on underrepresented groups. Outcome evaluation of the project’s research, education, and workforce development activities will be carried out using internal and external surveys for qualitative and quantitative data.The 3D heterogeneous integration of power electronics for high-performance computing will be realized by leveraging an interposer having integrated magnetic inductors with new spin spray deposited ferrites, advanced high-voltage GaN switches, a novel single-stage point-of-load power converter architecture, and integrated high-voltage constant-frequency phase-shift control circuits in CMOS. Spin spray deposition of ferrites enables integrated thick ferrite films on-chip with a high relative permeability of ~3000 from aqueous solutions with readily tailored compositions at low temperatures of ~90 degrees C for integrated inductors and transformers on Si, printed circuit board, or other substrates for integrated power electronics. The high-voltage enhancement-mode GaN devices will utilize 3D sculptured field management to achieve record power figure-of-merits. The single-stage point-of-load conversion architecture can maintain zero-voltage and near-zero current switching across wide voltage and power ranges and enables high power density with high and flat efficiencies. Co-design of the power conversion architecture, CMOS integrated-circuits-based control, high-performance GaN switches, interposer with integrated magnetic components, and magnetic materials will help achieve compact and highly efficient integrated backside point-of-load power electronics for high-performance computing. This convergent co-design will be conducted by a qualified team with complementary expertise, ranging from wide-bandgap semiconductor switches, magnetic materials and integrated magnetic components, CMOS control circuits, and power conversion architectures. This activity will also result in new co-design methodologies leveraging circuit simulation and multi-physics analysis, and design tools.This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.