FuSe/Collaborative Research: Heterogeneous Integration in Power Electronics for High-Performance Computing (HIPE-HPC)

用于计算的能源占全球能源消耗的2%以上，其中很大一部分浪费在向微处理器供电的最后阶段。因此，提高效率和减小尺寸（克服空间限制）是下一代高性能计算电力传输解决方案的主要目标。这就要求开关和电感能够支持更高的电压、电流和频率，同时损耗更低。硅（Si）互补金属氧化物半导体（CMOS）技术可以提供高水平的集成和控制，但Si CMOS开关具有更高的开关损耗。宽带隙半导体材料可以实现更好的开关，但它们不能轻易地与Si CMOS工艺集成。高性能功率传输解决方案还需要紧凑的集成电感，以支持更高的功率，更高的小型化频率和更低的核心损耗。这个半导体的未来（FuSe）项目利用CMOS技术和新的功率转换架构共同设计和异构集成宽带隙半导体器件和片上铁氧体电感器，以开发用于高性能计算的下一代集成功率传输系统。该项目将为高性能计算的高效后置集成电源传输系统提供技术基础，并提高美国在半导体制造业的竞争力，从而产生重大的科学和社会影响。该项目还将加强对研究生和本科生在半导体、磁学、电力电子、集成电路、高性能计算等核心技术的基本主题的教育。还计划了一个广泛的劳动力发展计划，以吸引学生到与该项目相关的领域，并教育已经在该行业工作的人，重点是代表性不足的群体。项目的研究、教育和劳动力发展活动的结果评估将使用内部和外部调查进行定性和定量数据。高性能计算的3D异构电力电子集成将通过利用集成了新型自旋喷涂沉积铁氧体的磁电感器、先进的高压GaN开关、新型单级负载点功率转换器架构以及集成在CMOS中的高压恒频移相控制电路的中间体来实现。自旋喷涂铁氧体沉积技术可以在~90℃的低温下，从易于定制的成分的水溶液中获得具有~3000高相对磁导率的片上集成厚铁氧体薄膜，用于集成电力电子器件的硅、印刷电路板或其他基板上的集成电感和变压器。高压增强型GaN器件将利用3D雕刻场管理来实现创纪录的功率特性。单级负载点转换架构可以在宽电压和功率范围内保持零电压和近零电流切换，并实现高功率密度和高平坦效率。功率转换架构、基于CMOS集成电路的控制、高性能GaN开关、集成磁性元件的中间层和磁性材料的协同设计将有助于实现紧凑、高效的集成后端负载点功率电子器件，用于高性能计算。这种融合的共同设计将由一个具有互补专业知识的合格团队进行，范围包括宽带隙半导体开关、磁性材料和集成磁性元件、CMOS控制电路和功率转换架构。这项活动还将产生新的协同设计方法，利用电路仿真和多物理场分析以及设计工具。该奖项反映了美国国家科学基金会的法定使命，并通过使用基金会的知识价值和更广泛的影响审查标准进行评估，被认为值得支持。

The energy utilized for computing is more than 2 percent of global energy consumption, and a substantial fraction of it is wasted in the final stages of power delivery to microprocessors. Hence, efficiency improvement and size reduction (to overcome space limitations) are the main objectives for the next generation of power delivery solutions for high-performance computing. These require switches and inductors that can support higher voltages, currents, and frequencies with lower losses. Silicon (Si) complementary metal-oxide semiconductor (CMOS) technology can provide a high level of integration and control, but Si CMOS switches have higher switching losses. Wide-bandgap semiconductor materials enable better switches, but they cannot be easily integrated with the Si CMOS process. High-performance power delivery solutions also require compact integrated inductors that can support higher power, higher frequencies for miniaturization, and lower core losses. This Future of Semiconductors (FuSe) project uses co-designing and heterogeneous integration of wide-bandgap semiconductor devices and on-chip ferrite inductors with CMOS technology and a new power conversion architecture to develop next-generation integrated power delivery systems for high-performance computing. The project will have a significant scientific and societal impact by contributing to the technological foundations of highly efficient backside integrated power delivery systems for high-performance computing and enhancing US competitiveness in semiconductor manufacturing. The project will also strengthen the education of graduate and undergraduate students on essential topics of semiconductors, magnetics, power electronics, integrated circuits, high-performance computing, among other core technologies. An extensive workforce development program is also planned to attract students to the fields related to this project and to educate people already working in the industry with an emphasis on underrepresented groups. Outcome evaluation of the project’s research, education, and workforce development activities will be carried out using internal and external surveys for qualitative and quantitative data.The 3D heterogeneous integration of power electronics for high-performance computing will be realized by leveraging an interposer having integrated magnetic inductors with new spin spray deposited ferrites, advanced high-voltage GaN switches, a novel single-stage point-of-load power converter architecture, and integrated high-voltage constant-frequency phase-shift control circuits in CMOS. Spin spray deposition of ferrites enables integrated thick ferrite films on-chip with a high relative permeability of ~3000 from aqueous solutions with readily tailored compositions at low temperatures of ~90 degrees C for integrated inductors and transformers on Si, printed circuit board, or other substrates for integrated power electronics. The high-voltage enhancement-mode GaN devices will utilize 3D sculptured field management to achieve record power figure-of-merits. The single-stage point-of-load conversion architecture can maintain zero-voltage and near-zero current switching across wide voltage and power ranges and enables high power density with high and flat efficiencies. Co-design of the power conversion architecture, CMOS integrated-circuits-based control, high-performance GaN switches, interposer with integrated magnetic components, and magnetic materials will help achieve compact and highly efficient integrated backside point-of-load power electronics for high-performance computing. This convergent co-design will be conducted by a qualified team with complementary expertise, ranging from wide-bandgap semiconductor switches, magnetic materials and integrated magnetic components, CMOS control circuits, and power conversion architectures. This activity will also result in new co-design methodologies leveraging circuit simulation and multi-physics analysis, and design tools.This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.