SHF: Medium: Provably Correct, Energy-Efficient Edge Computing

今天的通用处理器遵循冯·诺依曼模型，其中程序作为指令序列执行。然而，这种串行执行被证明是太慢了。因此，处理器寻求可以安全地并行执行的指令以增强性能。然而，在硬件中实现并行是极其复杂的。复杂性使得处理器效率低下且不安全，导致行业转向专门的硬件加速器，以非常好地运行特定程序。不幸的是，这些加速器是昂贵的和限制性的。为了解决这些问题，本项目提出后冯·诺依曼，低处理器，明确暴露程序并行性，大大简化硬件。通过新的编译软件和简化的并行硬件，该项目旨在显著提高能源效率和系统正确性。这些进步将超越冯·诺依曼模型的局限性，促进创新，同时提高性能、效率和安全性。这项研究将由一个多元化的团队进行，包括通过NSF本科生研究经验计划的本科生。此外，研究人员将开发一个推广计划，教育K-12教师和公众对各种计算模型。该奖项的关键技术创新是程序的先天并行处理器表示和一个简单的，空间实现的并行处理器。此外，空间架构采用分层的模块化方法，实现了多个维度的可扩展性。简单性和模块化允许编译器，体系结构和硬件实现的易处理的正式模型，允许调查人员证明正确性和安全性。所提出的架构从一开始就建立了安全性，而不是像研究人员目前努力为冯诺依曼架构做的那样，试图在事后证明安全性。模块化还通过将程序分解为具有良好定义的接口的更小的独立单元来实现可扩展编译，每个单元都可以有效地编译到所提出的架构上，并且还通过将数据与其对应的计算放在一起来实现近数据计算，以克服数据移动的成本上升。最终的处理器设计有望成为第一个可扩展的通用架构，具有可证明的正确性和安全性。该奖项反映了NSF的法定使命，并通过使用基金会的知识价值和更广泛的影响审查标准进行评估，被认为值得支持。

Today’s general-purpose processors follow the von Neumann model, where programs execute as a sequence of instructions. However, this serial execution proves to be too slow. Processors thus seek instructions that can safely execute in parallel to enhance performance. Yet, implementing parallelism in hardware is extremely complicated. The complexity renders processors inefficient and insecure, leading the industry's shift toward specialized hardware accelerators tailored to run specific programs exceptionally well. Unfortunately, these accelerators are costly and restrictive. To address these issues, this project proposes post-von Neumann, dataflow processors, that explicitly expose program parallelism to dramatically simplify hardware. Through new compilation software and simplified parallel hardware, the project aims to significantly improve energy efficiency and system correctness. These advancements will transcend von Neumann model limitations, fostering innovation while enhancing performance, efficiency, and security. The research will be conducted by a diverse team, including undergraduates through the NSF Research Experiences for Undergraduates program. Moreover, the investigators will develop an outreach program to educate K-12 teachers and the public on various computing models.The key technical innovation of this award is the innately parallel dataflow representation of programs and a simple, spatial implementation of a dataflow processor. Moreover, the spatial architecture adopts a hierarchical, modular approach that enables scalability in multiple dimensions. Simplicity and modularity admit tractable formal models of the compiler, architecture, and hardware implementation, allowing investigators to prove correctness and security. The proposed architecture builds in security from the beginning, rather than trying to prove security after the fact, as researchers currently struggle to do for von Neumann architectures. Modularity further enables scalable compilation by breaking programs into smaller, independent units with a well-defined interface, each of which can be efficiently compiled onto the proposed architecture, and also enables near-data computation by co-locating data with its corresponding computation to overcome the rising cost of data movement. The resulting processor design promises to be the first a scalable, general-purpose architecture with provable correctness and security.This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.