Collaborative Research: SaTC: CORE: Small: Secure and Robust Machine Learning in Multi-Tenant Cloud FPGA

随着云计算市场的快速增长和机器学习（ML）计算的关键发展，云FPGA（现场可编程门阵列）已成为公共租赁的重要硬件资源，多个租户可以共同驻留并随着时间甚至同时共享FPGA芯片。在多租户云FPGA环境中联合使用许多硬件资源的情况下，创建了独特的攻击面，其中恶意租户可以利用这种间接交互来操纵其他租户的电路应用，例如，故意注入错误。在先前的研究中已经证明，片外存储器和片上缓冲器之间ML模型参数传输的小但精心设计的扰动可能完全使ML智能失效，即使在黑盒攻击场景下，也会对未来ML云FPGA系统构成前所未有的威胁。本项目（1）旨在了解多租户ML云FPGA系统的脆弱性并探索防御方法，这对于云FPGA计算领域的工业界和学术界都是至关重要和及时的;（2）提高ML云系统的安全性，以防止基于硬件的模型篡改多租户云FPGA计算基础设施中的片外数据传输;以及（3）将研究成果与教育结合起来，包括新课程开发、本科生和研究生培训，以及通过K-12外展计划促进妇女和代表性不足的少数民族在STEM中的发展。该项目将ML算法安全和FPGA硬件安全相结合，遵循软硬件协同设计机制，探索提高多租户ML云-FPGA系统安全性的新解决方案。它包括三个研究重点。Thrust-1系统地研究、建模和表征了一种对抗性权重复制硬件故障注入方法，该方法利用恶意租户中的攻击性功率掠夺电路将故障注入受害租户的ML模型。Thrust-2探索了各种ML算法方法，以增强ML模型的内在鲁棒性和弹性，以防止在从片外存储器到片上缓冲器的传输过程中将对抗性故障注入模型参数。Thrust-3研究FPGA系统级防篡改方法，以进一步提供全面的解决方案来提高ML-FPGA系统安全性。该奖项反映了NSF的法定使命，并通过使用基金会的知识价值和更广泛的影响审查标准进行评估，被认为值得支持。

Alongside the rapid growth of cloud-computing market and critical developments in machine learning (ML) computation, the cloud-FPGA (Field Programmable Gate Arrays) has become a vital hardware resource for public lease, where multiple tenants can co-reside and share an FPGA chip over time or even simultaneously. With many hardware resources being jointly used in the multi-tenant cloud-FPGA environment, a unique attack surface is created, where a malicious tenant can leverage such indirect interaction to manipulate the circuit application of other tenants, e.g., intentionally injecting faults. It has been demonstrated in prior research that small, but carefully designed, perturbation of the ML model parameter transmission between off-chip memory and on-chip buffer could completely malfunction ML intelligence, even under black-box attack scenario, posing an unprecedented threat to future ML cloud-FPGA system. This project (1) targets to understand the vulnerability of multi-tenant ML cloud-FPGA systems and explore defensive approaches, which are crucial and timely for both industry and academia in the cloud-FPGA computing domain; (2) advances the security of ML cloud system against hardware-based model tampering on off-chip data transmission in multi-tenant cloud-FPGA computing infrastructure; and (3) integrates the research outcomes with education in terms of new curriculum development, undergraduate and graduate student training, as well as promoting women and underrepresented minorities in STEM through K-12 outreach programs. This project integrates ML algorithm security and FPGA hardware security to follow a software-hardware co-design mechanism, exploring novel solutions that improve the security of multi-tenant ML cloud-FPGA system. It consists of three research thrusts. Thrust-1 systematically studies, models, and characterizes an adversarial weight duplication hardware fault injection method, which leverages aggressive power-plundering circuits in malicious tenant to inject fault into the victim tenant's ML model. Thrust-2 explores various ML algorithmic methodologies to enhance the intrinsic robustness and resiliency of ML model against adversarial fault injection into model parameters during the transmission from off-chip memory to on-chip buffer. Thrust-3 investigates FPGA system-level tamper-resistant approaches to further provide comprehensive solutions to improve the ML-FPGA system security.This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.