Formal methods for the generation of power-safe test sets for digital circuits

点击翻译按钮获取中文摘要

The aim of this project is the development of a methodology for the generation of a power-safe test set for the production test of digital circuits. The test set should comply to the functional power specification of the circuit and prevent faults based on non functional power usage. Additionally, the test set should cover faults caused by high functional power peaks. Fault coverage loss should be prevented. A special focus should lie on the integration of layout information, which enables the incooperation of regional switching activity to prevent local IR drop. In order to guarantee a high fault coverage for hard to test circuits, SAT-based (optimization) methods should be developed as the underlying ATPG engine. It is assumed that these methods are able to process the large number of additional constraints more efficiently and, consequently, generate tests of higher quality than structural ATPG algorithms.