Development of a High-Performance Workstation with a Very-Long-Instruction-Word (VLIW) Processor

项目的主要成果总结如下：1。qa系列的评估和VLIW体系结构的重新设计：VLIW （Very Long Instruction Word）处理器，如qa系列，可以在指令执行过程中利用低级并行性。然而，它们有一个严重的缺点；也就是说，VLIW体系结构很难保持程序兼容性，因为它们的体系结构暴露给编译器。作为评估的结果，我们引入了一种新的处理器体系结构，SIMP（单指令流/多指令流水线），作为VLIW的一种偏差。假设提供了P条指令管道，SIMP处理器通过每个周期获取P条指令，理想地将每条指令的平均周期数减少到1/ P。它们可以同时保持程序的兼容性。SIMP处理器原型的开发：作为SIMP的第一个实现，我们开发了SIMP处理器原型。SIMP实现的性能增强程度取决于；1)如何连续、同时地提供多条指令，2)如何有效地解决数据和控制依赖关系。我们设计了依赖性解析和指令获取算法。依赖解析算法允许乱序执行具有动态代码调度的顺序指令流。静态代码调度的研究：虽然原型采用了动态代码调度，但它充分利用了静态代码调度的优势。静态和动态代码调度方法在各自的领域有所不同；例如，静态代码调度是通过对程序代码的广泛概述来完成的，而动态代码调度是通过窥视孔来完成的。然而，这些代码调度方法并不是相互排斥的。研究了跟踪调度、软件流水线调度、多循环调度等静态代码调度的适应性。

Main results of the project are summarized below.1. Evaluation of the QA-series and Redesign of VLIW Architecture:VLIW (Very Long Instruction Word) processors, such as the QA-series, can exploit low-level parallelism in the process of instruction execution. However, they have a serious drawback; i.e., it is difficult for VLIW architectures to keep program compatibility, because their architectures are exposed to compilers. As a result of the evalution, we have introduced a novel processor architecture, SIMP (Single Instruction stream/Multiple instruction Pipelining), as a deviation of VLIW. Given that P instruction pipelines are provided, SIMP porcessors ideally reduce the average number of cycles per instruction to 1/p by fetching P instructions per cycle. they can preserve program compatibility at the same time.2. Development of the SIMP Processor Prototype:As the first implementation of SIMP, we have developed the SIMP processor prototype. Degree of performance enhancement achieved by SIMP depends on; i) how to supply multiple instructions continuously and simultaneously, and ii) how to resolve data and control dependencies effectively. We have devised the algorithms for dependency resolution and instruction fetch. The dependency resolution algorithm permits out-of-order execution of sequential instruction stream with dynamic code scheduling.3. Studies on Static code Scheduling:Though the prototype employs dynamic code scheduling, it appreciates the advantage of static code scheduling. Static and dynamic code scheduling methods differ in their domain; i.e., static code scheduling is done with a broad overview of program codes, but dynamic code scheduling is done with a peephole. However, these code scheduling methods are not mutually exclusive. We have studied the adaptability of static code scheduling such as trace scheduling, software pipelining, polycyclic scheduling, and so on.