Performance Improvement by Exploiting Instruction-Level Parallelism

通过利用指令级并行性来提高性能

• 批准号: 02452166
• 负责人: TOMITA Shinji
• 金额: $ 3.65万
• 依托单位: Kyoto University (1991)Kyushu University (1990)
• 依托单位国家: 日本
• 项目类别: Grant-in-Aid for General Scientific Research (B)
• 财政年份: 1990
• 资助国家: 日本
• 起止时间: 1990 至 1991
• 项目状态: 已结题
• 来源: https://kaken.nii.ac.jp/en/grant/KAKENHI-PROJECT-02452166/
• 关键词: Superscalar processor; Instruction pipeline; Optimized compiler; Code scheduling; Branch prediction; Load; store architecture; Interrupt architecture; Low-level parallelism; ス-パ-スカラ・プロセッサ

The purpose of this research is to exploit parallelism at instruction level and to investigate various performance improvement techniques for superscalar architecture. Main results of the research are the following :l. Basic control mechanism for superscalar processorVarious techniques for improving the performance are proposed and verified to be effective by software simulation. These techniques include ; (1) Four-instruction-multiplexed pipelining scheme with in-order issue and out-of-order execution strategy. This scheme not only attains high-speed execution but also reduces hardware cost drastically. (2) Powerful branch prediction mechanism in which the branch target buffer and static branch prediction methods are combined. Together with the early branch resolution, this gives a great contribution to preventing control hazards. (3) New mechanism to escape imprecise interruption, (4) Static resolution method against load/store hazards.2. Optimizing compilerOptimizing compiler plays an essential role in improving the performance of superscalar processor. A software pipeline scheme, a loop-unrolling scheme and a powerful combination of these schemess are investigated and verified to be effective by simulation. Maximally 5 times higher performance can be gained.

本研究的目的是利用指令级的并行性，并研究各种用于超标量架构的性能改进技术。本文的主要研究成果如下：1。提出了各种改进性能的方法，并通过软件仿真验证了其有效性。这些技术包括；(1)具有有序发布和乱序执行策略的四指令复用流水线方案。该方案不仅实现了高速运行，而且大大降低了硬件成本。(2)强大的分支预测机制，将分支目标缓冲区和静态分支预测方法相结合。与早期分支决议一起，这对预防控制危害做出了巨大贡献。(3)避免不精确中断的新机制；(4)针对负载/存储危害的静态解析方法。优化编译器优化编译器对提高超标量处理器性能起着至关重要的作用。研究了一种软件管道方案、一种循环展开方案以及这三种方案的强大组合，并通过仿真验证了它们的有效性。最多可以获得5倍的性能提升。

项目成果

Kazuaki Murakami: "Trade-offs in Processor Design for Superscalar Architectures" Trans. IEICE. 74. 3883-3893 (1991)

Kazuaki Murakami：“超标量架构处理器设计的权衡”Trans。

久我 守弘: "SIMP(単一命令流/多重命令パイプライン)方式に基づくス-パスカラ・プロセッサ『新風』の性能評価" 情報処理学会「並列処理シンポジウムJSPP'90」. 337-344 (1990)

Morihiro Kuga：“基于 SIMP（单指令流/多指令管道）方法的超标量处理器“Shinpu”的性能评估”日本信息处理协会“并行处理研讨会 JSPP90”（1990）。

Akira Fukuda: "Toward Advanced Parallel Processing:Exproiting Parallelism at Task and Instruction Levels" IEEE MICRO. August. 17-31 (1991)

Akira Fukuda：“迈向高级并行处理：在任务和指令级别利用并行性”IEEE MICRO。

久我 守弘: "SIMP(単一命令流/多重命令パイプライン)方式に基づくス-パスカラ・プロセッサ『新風』の性能評価" 情報処理学会論文誌. 32. 817-827 (1991)

Morihiro Kuga：“基于 SIMP（单指令流/多指令管道）方法的超标量处理器“Shinpu”的性能评估”日本信息处理协会交易 32. 817-827（1991）。

Morihiro Kuga: "Performance Evaluation of the Superscalar Processor Based on the SIMP Architecture" Trans. IPSJ. 32. 817-827 (1991)

Morihiro Kuga：《基于SIMP架构的超标量处理器性能评估》Trans。