Performance Improvement by Exploiting Instruction-Level Parallelism

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The purpose of this research is to exploit parallelism at instruction level and to investigate various performance improvement techniques for superscalar architecture. Main results of the research are the following :l. Basic control mechanism for superscalar processorVarious techniques for improving the performance are proposed and verified to be effective by software simulation. These techniques include ; (1) Four-instruction-multiplexed pipelining scheme with in-order issue and out-of-order execution strategy. This scheme not only attains high-speed execution but also reduces hardware cost drastically. (2) Powerful branch prediction mechanism in which the branch target buffer and static branch prediction methods are combined. Together with the early branch resolution, this gives a great contribution to preventing control hazards. (3) New mechanism to escape imprecise interruption, (4) Static resolution method against load/store hazards.2. Optimizing compilerOptimizing compiler plays an essential role in improving the performance of superscalar processor. A software pipeline scheme, a loop-unrolling scheme and a powerful combination of these schemess are investigated and verified to be effective by simulation. Maximally 5 times higher performance can be gained.