The Architecture of a Next Gereration Hultimedia Server
The Architecture of a Next Gereration Hultimedia Server
批准号:
10558045
负责人:
TOMITA Shinji
金额:
$8.13万
依托单位:
依托单位国家:
日本
项目类别:
Grant-in-Aid for Scientific Research (B)
财政年份:
1998
资助国家:
日本
项目状态:
已结题
起止时间:
1998 至 1999
中文摘要
该项目包括以下三个主题:1。ReVolver/C40:一个体绘制架构我们开发了一个ReVolver/C40体绘制架构的原型,作为下一代多媒体服务器的可视化机制。体绘制是一种直接可视化体数据的方案,但由于内存上的银行冲突,难以实时执行。左轮手枪/C40有一个没有银行冲突的记忆系统。开发的原型机的评估结果表明,ReVolver/C40的渲染速度约为每秒6帧。一种控制驱动和数据驱动的混合处理器架构我们提出了双流作为下一代多媒体服务器的处理器架构。该体系结构不定义寄存器,指令直接传递操作数。超标量通过CAM实现指令调度逻辑,该逻辑可能成为系统的关键路径。Dualflow可以用RAM替换CAM。我们开发了一个编译器,并用SPEC基准对其进行了评估。结果表明,它插入了大量额外的指令,并且需要另一次优化来删除它们。Java字节码的高速执行下一代多媒体服务器需要Java字节码的高速执行。我们提出了一个值外置缓冲区。值暂存缓冲区存储过去执行的前后状态对。当机器状态与记忆的前状态匹配时,它可以通过用后状态替换它来消除执行。仿真研究结果表明,该算法最多可提高47.1%的速度。
英文摘要
The project consists of following three themes :1. ReVolver/C40: a volume rendering architectureWe developed a prototype of the ReVolver/C40 volume rendering architecture as a visualization mechanism for the next generation multimedia server. Volume rendering, which is a scheme to directly visualize volume data, is hard to execute in real-time because of bank conflict on the memory. ReVolver/C40 has a memory system free from bank conflict. The evaluation result of developed prototype shows that ReVolver/C40 can render about six frames per second.2. A hybrid processor architecture between control-and data-drivenWe proposed Dualflow as a processor architecture for the next generation multimedia server. The architecture does not define registers and the instructions pass operands directly. Superscalars implements the instruction scheduling logic with a CAM, and the logic may become the critical path of the system. Dualflow can replace the CAM with a RAM. We developed a compiler and evaluated it with the SPEC benchmark. The result shows it inserts a lot of extra instructions, and needs another optimization to remove them.3. High-speed Java bytecode executionHigh-speed execution of Java bytecode is necessary for the next generation multimedia server. We proposed a Value Look-aside Buffer. Value Look-aside Buffer memorizes pairs of pre-and post-states of the past executions. When the machine states matches one of the memorized pre-states, it can eliminate the execution just by replacing it with the post-state. The results of the simulation study shows it can speeds-up about 47.1% at best.
期刊论文(9)
专著(0)
科研奖励(0)
会议论文
登录
查看更多内容
古谷 直樹: "ボリュームレンダリング専用並列計算機 ReVolver/c40の性能評価" 情報研報. (1999)
Naoki Furuya:《体绘制并行计算机ReVolver/c40的性能评估》信息研究报告(1999)。
DOI:
--
发表时间:
期刊:
影响因子:
--
作者:
[]
通讯作者:
五島正裕: "Dualflowアーキテクチャの提案"並列処理シンポジウムJSPP2000. (2000)
Masahiro Goto:“双流架构的提议”并行处理研讨会 JSPP2000(2000)。
DOI:
--
发表时间:
期刊:
影响因子:
--
作者:
[]
通讯作者:
森 眞一郎: "並列計算機アーキテクトからみた計算機クラスタ" 情報処理. Vol.39 No.11. 46-50 (1998)
Shinichiro Mori:“从并行计算机架构师的角度来看计算机集群”信息处理第 39 卷第 46-50 期(1998 年)。
DOI:
--
发表时间:
期刊:
影响因子:
--
作者:
[]
通讯作者:
山本 孝伸: "超並列計算機JUMP-1のクラスタの実装及び予備的性能評価" 情報研報 98-ARC-130. 7-12 (1998)
Takanobu Yamamoto:“大规模并行计算机JUMP-1的集群实现和初步性能评估”信息研究报告98-ARC-130(1998)。
DOI:
--
发表时间:
期刊:
影响因子:
--
作者:
[]
通讯作者:
秤谷 雅史: "超並列計算機JUMP-1における分散共有メモリ管理の実装とその評価" 情報研報 98-ARC-130. 1-6 (1998)
Masashi Hazutani:“大规模并行计算机 JUMP-1 中分布式共享内存管理的实现和评估”信息研究报告 98-ARC-130 (1998)。
DOI:
--
发表时间:
期刊:
影响因子:
--
作者:
[]
通讯作者:
共 9 条
Real-Time Sensable Simulation Systems
-
批准号:16100001
-
项目类别:Grant-in-Aid for Scientific Research (S)
-
资助金额:$70.64万
-
财政年份:2004
-
负责人:TOMITA Shinji
-
依托单位:
Development of a network supercomputing environment with fine grain dynamic load distribution mechanism
-
批准号:12558027
-
项目类别:Grant-in-Aid for Scientific Research (B)
-
资助金额:$8.06万
-
财政年份:2000
-
负责人:TOMITA Shinji
-
依托单位:
A Research of Register-less Architecture for Next Generation High Performance Processors
-
批准号:12480072
-
项目类别:Grant-in-Aid for Scientific Research (B)
-
资助金额:$7.42万
-
财政年份:2000
-
负责人:TOMITA Shinji
-
依托单位:
The Architecture of A Flexible Supercomputer Integrating A Realtime Visualization Mechanism with 3-Dimensional Memories
-
批准号:06402059
-
项目类别:Grant-in-Aid for General Scientific Research (A)
-
资助金额:$18.94万
-
财政年份:1994
-
负责人:TOMITA Shinji
-
依托单位:
Prototype Development and Experimental Implementation of A Massively Parallel Computer
-
批准号:06508001
-
项目类别:Grant-in-Aid for Developmental Scientific Research (A)
-
资助金额:$51.65万
-
财政年份:1994
-
负责人:TOMITA Shinji
-
依托单位:
Research on a Reconfigurable Parallel Computer
-
批准号:02555071
-
项目类别:Grant-in-Aid for Developmental Scientific Research (B)
-
资助金额:$11.26万
-
财政年份:1990
-
负责人:TOMITA Shinji
-
依托单位:
Performance Improvement by Exploiting Instruction-Level Parallelism
-
批准号:02452166
-
项目类别:Grant-in-Aid for General Scientific Research (B)
-
资助金额:$3.65万
-
财政年份:1990
-
负责人:TOMITA Shinji
-
依托单位:
Study of a Reconfigurable Parallel Processor
-
批准号:62460129
-
项目类别:Grant-in-Aid for General Scientific Research (B)
-
资助金额:$3.71万
-
财政年份:1987
-
负责人:TOMITA Shinji
-
依托单位:
Development of a High-Performance Workstation with a Very-Long-Instruction-Word (VLIW) Processor
-
批准号:62850062
-
项目类别:Grant-in-Aid for Developmental Scientific Research
-
资助金额:$14.85万
-
财政年份:1987
-
负责人:TOMITA Shinji
-
依托单位:
海外基金