Research on a Reconfigurable Parallel Computer

可重构并行计算机的研究

• 批准号: 02555071
• 负责人: TOMITA Shinji
• 金额: $ 11.26万
• 依托单位: Kyoto University (1991)Kyushu University (1990)
• 依托单位国家: 日本
• 项目类别: Grant-in-Aid for Developmental Scientific Research (B)
• 财政年份: 1990
• 资助国家: 日本
• 起止时间: 1990 至 1991
• 项目状态: 已结题
• 来源: https://kaken.nii.ac.jp/grant/KAKENHI-PROJECT-02555071/
• 关键词: Reconfigurable Architecture; Parallel Computer; Synchronization; Cache Coherence; Parallel Language; Load Balance; Parallel Operating System; Message Driven

The purpose of this research is to improve the performance of a parallel computer by narrowing the gap between the logical structure of problems and the physical hardware structure. The prototype computer called KRPP, has been built. The main results of the research are the following :1. Reconfigurable interconnection networkKRPP consists of 128 SPARC microprocessors (PEs) which are connected by a crossbar network. In order to control the network, two basic modes demand and preset modes, . are prepared. These wde provide reconfigurability by which the network structure can be tailored to a wide range of applications. A network synthesis compiler is also developed.2. Element processorKRPP employs a NUMA memory architecture. In order to assure cache coherence for inter PEs and intra PE, a directory based cache coherence protocol and a scheme based on the reverse translation buffer method are implemented.3. Basic softwareA parallel programming language which is an extension of C language and a parallel operating system are also developed. The OS is particularly suited to a tightly coupled multiprocessor and has many features : The OS kernel function itself can be performed in parallel and a high-speed processor allocation mechanism for multiple threads is provided.

本研究的目的是通过缩小问题的逻辑结构和物理硬件结构之间的差距来提高并行计算机的性能。被称为KRPP的原型计算机已经建成。主要研究结果如下：1.可重构互连网络KRPP由128个可重构微处理器（PE）组成，它们通过交叉开关网络连接在一起。为了控制网络，有两种基本模式需要和预置模式。都准备好了这些wde提供了可重构性，通过该可重构性，网络结构可以针对广泛的应用进行调整。开发了网络综合编译器.单元处理器KRPP采用NUMA存储器体系结构。为了保证PE间和PE内的Cache一致性，实现了基于目录的Cache一致性协议和基于反向转换缓冲区方法的Cache一致性方案.基础软件开发了C语言的并行程序设计语言和并行操作系统。该操作系统特别适合于紧密耦合的多处理器，并具有许多功能：操作系统内核功能本身可以并行执行，并提供了多线程的高速处理器分配机制。

项目成果

Shin-ichiro Mori: "The Kyushu University Reconfigurable Parallel Processor -Cache Architecture and Cache Coherence Schenes-" Proc.of International Symposium on Shered Memory Multiprocessing. (1991)

Shin-ichiro Mori：“九州大学可重构并行处理器 - 缓存架构和缓存一致性方案 -”Proc.of 国际共享内存多处理研讨会。

岩田 英次: "可変構造型並列計算機のキャッシュ・ア-キテクチャ-キャッシュ構成およびキャッシュ内コヒ-レンス処理-" 情報処理学会論文誌. 32. 777-789 (1991)

Eiji Iwata：“可变结构并行计算机的缓存体系结构 - 缓存配置和缓存内一致性处理”日本信息处理学会汇刊 32. 777-789 (1991)。

Shinーichiro Mori: "The Kyushu University Reconfigurable Parallel ProcessorーCache Architecture and Cache Coherence Schenesー" Proc.of International Symposium on Shered Memory Multiprocessing. (1991)

Shin－ichiro Mori：“九州大学可重构并行处理器－高速缓存架构和高速缓存一致性方案－”Shered Memory Multiprocessing国际研讨会论文集（1991）。

Akira Fukuda: "Toward Advanced Parallel Processing:Exproiting Parallelism at Task and Instruction Levels" IEEE MICRO. August. 17-31 (1991)

Akira Fukuda：“迈向高级并行处理：在任务和指令级别利用并行性”IEEE MICRO。

Shinji Tomita(J.Kondo(ed)Super-Computing): "Computer Architecture in the 1990s" Springer-Verlag, 215 (1991)

Shinji Tomita（J.Kondo（ed）超级计算）：“1990 年代的计算机架构”Springer-Verlag，215（1991）