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Study of a Reconfigurable Parallel Processor

可重构并行处理器的研究

基本信息

批准号：
62460129
负责人：
TOMITA Shinji
金额：
$ 3.71万
依托单位：
Kyushu University
依托单位国家：
日本
项目类别：
Grant-in-Aid for General Scientific Research (B)
财政年份：
1987
资助国家：
日本
起止时间：
1987 至 1988
项目状态：
已结题

项目摘要

Main results in the project are as follows.1.Studies on reconfigurableinterconnection networks. A crossbar network is chosen to attain arbitrary interconnection topologies. The network allows users to match a interconnection topology to a given algorithm. The modular 128X128 crossbar network is implemented by arranging 256 identical 8X8 crossbar LSI-modules in a 16X16 matrix form. A method where the network has switching patterns is proposed to prevent any contention from occurring at run time. By employing the method, high-speedinter-processor communication can be attained.2.Development of processing elements. Reconfigurable memory architecture is implemented. The architecture allows the system to be reconfigured as a loosely coupled multiprocessor or a tightly coupled multiprocessor.3.Development of a reconfigurable parallel processor. Message transmission between processors is pipelined to attain high-speed inter-processor communication. A reconfigurable parallel processor which employs the above architecturesis developed.4. Studies on dynamic load balancing scheme. Task/thread-model is chosen as a good parallel processing model in a tightly coupled multiprocessor. A load balancing scheme where processor assign a task is proposed. By using the scheme, loads in the system can be distributed between processors, and overhead during context switching can be reduced. A high-level programming language which allows users to describe parallel processing models effectively and its language processor are developed.

本课题的主要研究成果如下：1.可重构互连网络的研究。选择交叉开关网络以获得任意互连拓扑。该网络允许用户将互连拓扑与给定算法相匹配。模块化128 × 128交叉开关网络通过以16 × 16矩阵形式布置256个相同的8 × 8交叉开关LSI模块来实现。提出了一种网络具有切换模式的方法，以防止在运行时发生任何争用。采用这种方法，可以实现处理器间的高速通信。2.处理单元的开发。实现了可重构存储器结构。该体系结构允许系统重新配置为松耦合多处理器或紧耦合多处理器。3.可重构并行处理器的开发。处理器间的消息传输采用流水线方式，以实现处理器间的高速通信。设计了一个采用上述结构的可重构并行处理器.动态负载平衡方案的研究。任务/线程模型是紧耦合多处理机中较好的并行处理模型。提出了一种处理器分配任务的负载均衡方案。通过使用该方案，可以在处理器之间分配系统中的负载，并且可以减少上下文切换期间的开销。开发了一种能有效描述并行处理模型的高级程序设计语言及其语言处理器。