Investigation on gate insulators for InP MIS field effect transistors with in-situ photo-CVD

到去年年底，我们已经成功地制作出了具有较好性能的InP MISFET。为了获得更好的场效应管，我们研究了InP表面性质与栅绝缘层种类和制备InP MISFET的工艺条件之间的关系。由于InP表面不需要形成电极，因此采用激光拉曼光谱和光致发光方法对InP表面进行表征。通过测量声子频率的额外位移，可以估计半导体中的应力，清楚地表明，与SiO_2或Si_3N_4薄膜的InP具有约10^9dyn/cm~2的拉应力，而InP与光-CVD沉积的PN薄膜的拉应力可以忽略不计。表面复合速度可以通过对拉曼光谱测量的LO声等离子体耦合模的分析来估计。在较低温度(150ﾟC)下光化学气相沉积方法沉积的Pn膜表面硫化处理后，InP与Pn膜的表面复合速度比SiO_2或Si_3N_4膜的InP小一个数量级。这一结果得到了光致发光和C-V方法的支持，并将对确定高质量InP MISFET的最佳工艺条件具有重要意义。

We have succeeded to fabricate InP MIS FETs with relatively good properties by the end of the last year. This year we investigated correlations between properties of InP surface and kinds of gate insulator or process conditions of fabricating InP MIS FET in order to get much better FETs.Laser Raman spectroscopy and photoluminescence method were used to characterize InP surface because formation of electrodes are not necessary in these methods.Stress in semiconductors can be estimated based on extra shift of a phonon frequency which is measured clear that InP with SiO_2 or Si_3N_4 film has tensile stress in the order of 10^9 dyn/cm^2 while InP with PN film deposited by photo-CVD has negligible stress.Surface recombination velocity can be estimated from the analysis of LO phononplasmon coupled mode which is measured by Raman spectroscopy. Surface recombination velocity of InP with PN film deposited by photo-CVD method at a relatively low temperature such as 150ﾟC after sulfer treatment of InP surface was smaller than those of InP with SiO_2 or Si_3N_4 film by about one order. The results were supported by photoluminescence and C-V methods and will have important roles in determining optimum conditions of fabricating InP MISFETs with high quality.