A Study on fully inverted SIMOX MOSFETs

SOI MOSFET的电气特性是由设备sirnulator CADDETH调查的，发现阈值电压降低到1（v）和短通道效应被完全反转（F1）SOI MOSFETs，由作者提出的。FI（完全反转）SOI MOSFET是一种新颖的SOI MOSFETs类型，顶部硅层的整个区域都是完全反转的。在FI SOI MOSFET中，被耗尽的区域被设计成顶层硅层，门电场指数在通道中收费比完全耗尽的（FD）SOI MOSFET<s。在情况下， FI SOI MOSFET预计将具有阈值电压（VIE D2）的优势，可以保持低密度高的多普勒，也可以使短通道效应受到抑制。在FI SOI MOSFETs中，被耗尽的区域被设计成顶层硅层，而门电场指数在通道中收费比完全耗尽的（FD）SOI MOSFETs更有效。在consequence中，发现了FI SOI MOSFETs，threshold voltage（Vy-D2）可以是lowered keepnig dopant density high，也可以是off of Vy-D2 th-D2也可以是suppressed substantially。SOI MOSFETs is shown in the figure. When the thickness of top Si layer（t-D2Si-D2）is less than 10（nm）， and MOSFET is in FI mode， the dependence of V-D2th-D2 on t-D2 is suppressed remarkably. FI SOI MOSFET can realize high packing density， short signal propagation delay， together with a low voltage power supply less than 1 V， and are one of the most feasible devices for low power VLSI。

Electrical characteristics of SOI MOSFETs was investigated by the device sirnulator CADDETH and it is found that threshold voltage is reduced to aroud 1(v)and short channel effect was suppressed by Fully Inverted (F1)SOI MOSFETs, which were proposed by the authors.The FI(fully inverted)SOI MOSFET is a novel type of SOI MOSFETs where the whole region of the top silicon layer is inverted completely. In FI SOI MOSFETs, the depleted region is eliminated by thinning the top silicon layer, and the gate electric field induces charge in the channel more effectively than in the fully depleted(FD)SOI MOSFET<s. In consequence, FI SOI MOSFETs are expected to have advantages that the threshold voltage(VィイD2thィエD2)can be lowered maintaining dopant density high and also the short channel effect can be suppressed substantially. In FI SOI MOSFETs, the depleted region is eliminated by thinning the top silicon layer, and the gate electric field induces charge in the channel more effectively than in the fully depleted(FD)SOI MOSFETs. In consequence, it is found that in FI SOI MOSFETs, the threshold voltage(VィイD2thィエD2)can be lowered keepnig dopant density high and also the roll-off of VィイD2thィエD2 can be suppressed substantially. The behavior of VィイD2thィエD2 in SOI MOSFETs is shown in the figure. When the thickness of top Si layer(tィイD2SiィエD2)is less than 10(nm), and MOSFET is in FI mode, the dependence of VィイD2thィエD2 on tィイD2SiィエD2 is suppressed remarkably.FI SOI MOSFETs can realize high packing density, short signal propagation delay, together with a low voltage power supply less than 1V, and are one of the most feasible devices for low power VLSI.