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Fabrication of Digital Circuits by self-formation of atomic layr steps

Fabrication of Digital Circuits by self-formation of atomic layr steps
通过原子层台阶自形成数字电路的制造
批准号:
07555112
负责人:
SUGANO Takuo
金额:
$4.03万
依托单位:
依托单位国家:
日本
项目类别:
Grant-in-Aid for Scientific Research (A)
财政年份:
1995
资助国家:
日本
项目状态:
已结题
起止时间:
1995 至 1997

项目摘要

项目成果

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中文摘要
翻译
将硅表面原子层台阶/平台技术应用于无光刻的超小电容阵列制备技术中,已经制备出了控制硅表面自组织现象的装置。它包括扫描隧道显微镜(STM)系统,包括H-自由基枪、K细胞和原子力显微镜(AFM)。探索了利用该装置制作超微结构,通过在超高真空条件下对Si(100)衬底进行小偏移量的退火,实现了单原子层或双原子层的高可控性形成。样品通过电流被加热,并且Si(100)衬底的偏移角朝向<011>方向。利用(100)面偏置的硅衬底成功地制作了矩形叠瓦式双原子层/阶梯结构,并用扫描隧道显微镜(STM)对该结构进行了观察。利用各向异性刻蚀技术还获得了更大尺寸的矩形叠瓦状阶梯/阶梯结构,并用原子力显微镜进行了观察。
英文摘要
Application of atomic layr step/terrace on Si surface to fabrication technology of ultra small capacitance array without using lithography.Set up for controlling self-organization phenonena on Si surfaces was already prepared. It contained STM (Scanning Tunnel Microscope) system including H-radical gun, K-cell and AFM (Atomic Force Microscope). Fabrication of ultra-small structures using this set up is explored.Formation of single or double atomiclayr steps was achieved with high cotrollability by annealing of Si (100) substrates with small off-set under ultra-high vacuum condition. Samples were heated by passing current through them and the off-set angles of Si (100) substrates are toward <011> direction. Fabrication of rectangular imbricate two atomic layr step/terrace structure using silicon substrate with (100) surface off setting <011> direction was succeeded, and this structure was observed by STM (Scanning Tunnel Microscope). More large-scale rectangular imbricate step/terrace structure was also obtained using anisotropic etching of Si substarte, and it was observed by AFM (Atomic Force Microscope).
期刊论文(17)
专著(0)
科研奖励(0)
会议论文
T.Hanajiri,R.Shimizu T.Sugano: ""Formation of Ultra-small Structures on Si utilizing self-organization for Fabrication of Single Electron Devices"" Proc.of 2nd Symposium on Atumic Scale Structnre and Interface Dynamics. 39-40 (1998)
T.Hanajiri、R.Shimizu T.Sugano:“利用自组织在硅上形成超小型结构,用于单电子器件的制造”第二届原子尺度结构和界面动力学研讨会论文集。
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通讯作者:
鈴木,花尻,菅野: "「4端子単電子素子の作製プロセス」" 第58回応用物理学会学術講演会予稿集. II. 58 (1997)
铃木、花尻、菅野:“四端单电子器件的制造过程”第 58 届日本应用物理学会年会论文集 II(1997 年)。
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通讯作者:
T.Hanajiri, T.Toyabe, T.Sugano: "“Performances of Single Electron Devices with Asymmetric Tunnel Barriers"" Proc.of 3rd Int.Workshop on Quantum Functional Devices. 65-66 (1997)
T.Hanajiri、T.Toyabe、T.Sugano:“具有不对称隧道势垒的单电子器件的性能”,第三届国际量子功能器件研讨会论文集 65-66 (1997)。
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通讯作者:
Y.Matsumoto,T.Hanajiri,T.Toyabe,T.Sugano: ""Advantages of the Asymmetric Tunnel Barrier for High Density Integration of Single Electron Devices"" Proc.of Int.Symp.on Foramation,Physics snd Device Apprication of Quantum Structures. 144- (1996)
Y.Matsumoto,T.Hanajiri,T.Toyabe,T.Sugano:““单电子器件高密度集成的非对称隧道势垒的优点””Proc.of Int.Symp.on Foramation、Physics snd Device Apparation of Quantum
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17
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