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Coplanar type Silicon-Coupled Superconductine Three Terminal Devices

共面型硅耦合超导三端器件

基本信息

批准号：
61460123
负责人：
SUGANO Takuo
金额：
$ 3.71万
依托单位：
Unicersity of Tokyo
依托单位国家：
日本
项目类别：
Grant-in-Aid for General Scientific Research (B)
财政年份：
1986
资助国家：
日本
起止时间：
1986 至 1987
项目状态：
已结题

项目摘要

Coplanar silicon-coupled Josephson juctions with recessed electrode structure were fabricated using a new planarization process. Niobium was used as superconducting electrode's material, and silicon, doped to degenerate in order to avoid freeze-out of carriers at liquid helium temperature, was used as the bridge connecting two superconducting electrodes. The electrode spacing was about 0.1 <micrn>. The fabrication procedure is as follows.First, an n-type silicon wafer with (100) surface orientation was soped with boron to make p^+ thin layer on the surface. The boron doping was caried out by thermal diffusion using BN as dopant source at 1100゜c for 10 min. The junction depth and the surface concentration were estimated to be about 0.8 <micrn> and 4X10^<20> cm^-3, respectively.The planarization process is as follows. (1)Polymethyl methacrylate (PMMA) was spun onto the doped silicon wafer. A fine line was delineated using electron beam, and a resist stencil was formed. (2)An aluminium li … More ne of about 0.1 <MU>m in width was formed by thermal evaporation of aluminium onto the stencil and subsequent lift-off of the stencil by soaking in acetone. (3)This line was used as a mask for the reactive ion etchin of silicon using CCl_2F_2 gas. The etching depth was 0.2 <micrn>. The aluminium mask was removed after etching silicon. (4) Niobium of 150 nm in thickness was deposited by electron beam evaporation. (5) By spinning polymer onto the wafer, the surface of the wafer was planarized. The thickness of the polymer was about 300 nm. (6) The polymer was etched using O_2 plasma, and the etching was stopped just after the niobium on top of the fine line appeared from the polymer layer. (7)The niobium on the line was etched using reactiv ion etching by CCl_2F_2 gas. (8)The remaining polymer layer was removed.After obtaining the coplanar structure, niobium electrode was patterned using photolithography and reactive ion etching with CF_4 gas.Electrical measurements were performed on the devices at liquid helium temperature and the operation of the devices was confirmed. The typical value of I_CR_N product was 10 <micrn>v. The critical current versus temperature was measured for silicon-coupled Josephson junction (B) and the coherence lenght of superconducting electrons in silicon was estimated to be 23 nm at 7.8 K.Short channel MOS FETs with coplanar niobium electrodes were fabricated using the above described process and shallow doping technique. The channel length was 0.2 <micrn>m. The operation of The MOS FETs were confirmed at room temperature. Less

采用一种新的平坦化工艺制备了具有凹电极结构的共面硅耦合约瑟夫森结。采用Nb作为超导电极材料，用掺杂简并的硅作为连接两个超导电极的桥梁，以避免在液氦温度下载流子冻结。电极间距约为0.1微米。制备过程如下：首先，在(100)面取向的n型硅片上浸渍硼，在其表面形成p^+薄层。以氮化硼为掺杂源，在1100゜℃下热扩散10min，实现了硼的掺杂。结深和表面浓度分别约为0.8微米和4×10微米/平方厘米。(1)将聚甲基丙烯酸甲酯(PMMA)纺丝到掺杂硅片上。用电子束勾画出一条细小的线，形成了抗蚀剂模板。(2)一辆铝制锂…更多的Ne的宽度约为0.1&lt；MU&gt；m，是通过将铝热蒸发到模板上，然后通过浸泡在丙酮中将模板剥离而形成的。(3)用这条线作为掩模，用CCl_2F_2气体对硅进行反应离子刻蚀。刻蚀深度为0.2微米。在刻蚀硅之后，铝掩模被移除。(4)用电子束蒸发沉积了厚度为150 nm的Nb。(5)通过将聚合物纺丝到晶片上，使晶片表面平坦化。聚合物的厚度约为300 nm。(6)用O_2等离子体刻蚀聚合物，当聚合物层中出现细线顶端的Nb时，停止刻蚀。(7)用CCl_2F_2气体反应离子刻蚀的方法刻蚀线上的Nb。(8)去除剩余的聚合物层，得到共面结构后，采用光刻和CF4气体反应离子刻蚀的方法制作Nb电极，在液氦温度下对器件进行电学测量，确认器件的工作状态。测量了硅耦合约瑟夫森结(B)的临界电流随温度的变化，并估算了7.8K时硅中超导电子的相干长度为23 nm。采用上述工艺和浅掺杂技术制备了具有共面Nb电极的短沟道MOS FET。沟道长度为0.2微米。在室温下证实了MOS FET的工作。较少