权益分类	功能权益	普通用户	{{item.name}}会员
{{category.name}}	{{benefitItem.name}}

Research on Single Electron Tunnel Device using substrates with small misorientations

小取向差衬底单电子隧道器件研究

基本信息

批准号：
05452200
负责人：
SUGANO Takuo
金额：
$ 4.74万
依托单位：
Toyo University
依托单位国家：
日本
项目类别：
Grant-in-Aid for General Scientific Research (B)
财政年份：
1993
资助国家：
日本
起止时间：
1993 至 1995
项目状态：
已结题

项目摘要

(1) Formation of step-terrace structures using Si surface with small misorientationsFormatio of Single or Double atomiclayr steps was achieved with high cotrollability by annealing of Si (100) substrates with small misorientations under ultra-high vacuum condition. Samples were heated by passing current through them and the misorientation angles of Si (100) substrates are 4ﾟ and 1ﾟ toward (110) direction.(2) Design and fablication of single electron transistor using a small island surrounded by group of surfaces with same orientationThe fablication process of single electron transistor favarable for dense integration was proposed. Principle points of this fablication process were as followed. Firstly, the inversion layr formed by electric field was used for quantum dot. Secondly, the area of inversion layr was reduced using recess structure surrounded by (111) surfaces with single or double atomiclayr steps. Finally, the recess structure was fablicated by both anisotropic etching of Si … More (100) substarte and annealing the substrate under ultara-high vacuum condition.Device performance of this single electron transistor was simulated by 2-dimentional capacitance analysis and the optimum device scale was estimated. Single electron transistor with this scale was fablicated and its electrical properties also characterized.In addition, electron beam lithography process was examined for further scale down of this device and fablication of 0.05mum line pattern was achieved.(3) Design and fablication of single electron device with asymmetric tunnel barrierSingle electron device with asymmetric tunnel barrier was proposed and its performance was simulated. It was demonstrated that directionality of tunneling current and less correlation between capacitance and resistanece makes it easy to fablicate single electron device with high performance.Furthermore, it was made clear that asymmetric tunnel barrier have advantages for realizing of not only boolean logic but also non boolean logic like binary decission diagram (BDD). Less

(1)利用小取向差的Si表面形成台阶-平台结构在超高真空条件下，通过对小取向差的Si（100）衬底进行退火处理，实现了高可控性的单原子层或双原子层台阶的形成。通过通电加热样品，得到Si（100）衬底的取向差角分别为4 °和1 °。(2)利用同向面群包围的小岛设计和制造单电子晶体管提出了有利于密集集成的单电子晶体管制造工艺。该制造过程的要点如下。首先，利用电场形成的反型层作为量子点。第二，采用单原子层或双原子层台阶的（111）面包围的凹槽结构，减小了反型层的面积。最后，通过对Si的各向异性刻蚀和对Si的各向异性刻蚀， ...更多信息 (100)在超高真空条件下对衬底进行退火，用二维电容分析法模拟了这种单电子晶体管的器件性能，并估算了最佳器件尺寸。制作了该尺寸的单电子晶体管，并对其电性能进行了表征，同时对电子束光刻工艺进行了研究，实现了0.05 μ m线图形的制作。(3)非对称隧道势垒单电子器件的设计与制作提出了非对称隧道势垒单电子器件，并对其性能进行了模拟。证明了隧穿电流的方向性和电容与电阻之间较小的相关性使单电子器件的制作变得容易，并进一步说明了非对称隧穿势垒不仅有利于布尔逻辑的实现，而且有利于二进制判定图（BDD）等非布尔逻辑的实现。少