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Research on Single Electron Tunnel Device using substrates with small misorientations

Research on Single Electron Tunnel Device using substrates with small misorientations
小取向差衬底单电子隧道器件研究
批准号:
05452200
负责人:
SUGANO Takuo
金额:
$4.74万
依托单位:
依托单位国家:
日本
项目类别:
Grant-in-Aid for General Scientific Research (B)
财政年份:
1993
资助国家:
日本
项目状态:
已结题
起止时间:
1993 至 1995

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中文摘要
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英文摘要
(1) Formation of step-terrace structures using Si surface with small misorientationsFormatio of Single or Double atomiclayr steps was achieved with high cotrollability by annealing of Si (100) substrates with small misorientations under ultra-high vacuum condition. Samples were heated by passing current through them and the misorientation angles of Si (100) substrates are 4゚ and 1゚ toward (110) direction.(2) Design and fablication of single electron transistor using a small island surrounded by group of surfaces with same orientationThe fablication process of single electron transistor favarable for dense integration was proposed. Principle points of this fablication process were as followed. Firstly, the inversion layr formed by electric field was used for quantum dot. Secondly, the area of inversion layr was reduced using recess structure surrounded by (111) surfaces with single or double atomiclayr steps. Finally, the recess structure was fablicated by both anisotropic etching of Si … More (100) substarte and annealing the substrate under ultara-high vacuum condition.Device performance of this single electron transistor was simulated by 2-dimentional capacitance analysis and the optimum device scale was estimated. Single electron transistor with this scale was fablicated and its electrical properties also characterized.In addition, electron beam lithography process was examined for further scale down of this device and fablication of 0.05mum line pattern was achieved.(3) Design and fablication of single electron device with asymmetric tunnel barrierSingle electron device with asymmetric tunnel barrier was proposed and its performance was simulated. It was demonstrated that directionality of tunneling current and less correlation between capacitance and resistanece makes it easy to fablicate single electron device with high performance.Furthermore, it was made clear that asymmetric tunnel barrier have advantages for realizing of not only boolean logic but also non boolean logic like binary decission diagram (BDD). Less
期刊论文(30)
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会议论文
Y.Matsumoto, T. Hanajiri, T. Toyabe and T. Sugano: "Single electron device with asymmetric tunnel barriers" Jpn. J. Appl. Phys.35. 655-660 (1996)
Y.Matsumoto、T. Hanajiri、T. Toyabe 和 T. Sugano:“具有不对称隧道势垒的单电子器件”Jpn。
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通讯作者:
坂上、花尻、菅野 他: "リセス構造を用いた単電子トランジスタ" 第43回応用物理学関係連合講演会予稿集. 第II分冊. (1996)
Sakagami、Hanajiri、Kanno 等人:“使用凹进结构的单电子晶体管”第 43 届应用物理协会会议论文集第二卷(1996 年)。
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石橋幸治: "半導体ナノ構造における電子輸送" 応用物理. 63. 104-115 (1994)
Koji Ishibashi:“半导体纳米结构中的电子传输”应用物理 63. 104-115 (1994)。
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T.Sugano: "Future Prospects of Devices for LSI" IEICE Trans.Electronics. E76-C. 1029-1033 (1993)
T.Sugano:“LSI 器件的未来前景”IEICE Trans.Electronics。
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17
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    • 项目类别:
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    • 资助金额:
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    • 财政年份:
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    • 资助金额:
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    • 财政年份:
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