Researches on the Design of Highly Reliable High-Speed Arithmetic Circuits with Redundant Coding

高可靠冗余编码高速运算电路设计研究

• 批准号: 63460134
• 负责人: YAJIMA Shuzo
• 金额: $ 4.1万
• 依托单位: KYOTO UNIVERSITY
• 依托单位国家: 日本
• 项目类别: Grant-in-Aid for General Scientific Research (B)
• 财政年份: 1988
• 资助国家: 日本
• 起止时间: 1988 至 1989
• 项目状态: 已结题
• 来源: https://kaken.nii.ac.jp/en/grant/KAKENHI-PROJECT-63460134/
• 关键词: Arithmetic Circuits; Hardware Algorithm; Fault-Tolerant Design; On-Line Error Detection; Logic Simulation; Fault Simulation; Test Generation; Redundant Coding; ハードウェアアルゴリズム; 論理シミュレーション; 故障シミュレーション

We conducted researches for the design of highly reliable high-speed arithmetic circuits with redundant coding.For (1) hardware algorithms for arithmetic operations with redundant coding and fault torelant design of circuits based on them and.(2) design verification of circuits and test generation, we got the following research results:1. We designed an on-line error-detectable fast array divider based on a division algorithm with a redundant binary representation and a residue code which we had previously proposed.2. We proposed a fast hardware algorithm for modular multiplication with a redundant representation. Modular multiplication with a large modulus is widely used in public key cryptosystems.3. We clarified various properties of the redundancy of a redundant binary representation.4. We proposed a time-symbolic simulation method as a new method for timing verification of logic circuits. We also implemented a simulator based on the method and a result analysis system.5. We designed an algorithm for satisfiability problems of regular temporal logic, which we had proposed before for formal verification.6. We presented a dynamic two-dimensional parallel method for fast fault simulation using a vector processor and implemented a fault simulator based on the method. We also presented a test pattern generation method using random patterns and implemented a program based on the method.7. We showed an efficient method for locally exhaustive testing of combinational circuits using linear logic circuits.We also researched on a method for generating prime implicants of logic functions, a representation method for logic functions and a hardware design language and got some results.

本文对高可靠性高速冗余编码算术电路的设计进行了研究，主要包括：（1）冗余编码算术运算的硬件算法及基于该算法的电路容错设计; (2)电路的设计验证和测试生成，取得了以下研究成果：1。在提出的冗余二进制表示和留数码除法算法的基础上，设计了一种可在线检测错误的快速阵列除法器.提出了一种基于冗余表示的模乘快速硬件算法。大模乘运算在公钥密码系统中有着广泛的应用.我们澄清了冗余二进制表示的冗余的各种属性。本文提出了一种新的逻辑电路时序验证方法--时间符号模拟法。并实现了基于该方法的模拟器和结果分析系统.我们设计了一个正则时态逻辑可满足性问题的算法，这个算法是我们以前在形式验证中提出的.提出了一种基于矢量处理器的动态二维并行快速故障模拟方法，并实现了一个基于该方法的故障模拟器。提出了一种基于随机模式的测试模式生成方法，并实现了基于该方法的测试模式生成程序.给出了一种利用线性逻辑电路进行组合电路局部穷举测试的有效方法，并对逻辑函数素蕴涵式的生成方法、逻辑函数的表示方法和硬件设计语言进行了研究，得到了一些结果。

项目成果

石浦菜岐佐: "ベクトル計算機による高速故障シュミレ-ションのための動的二次元並列法" 情報処理学会論文誌. 29. 522-528 (1988)

Nagisa Ishiura：“使用矢量计算机进行高速故障模拟的动态二维并行方法”，日本信息处理学会会刊 29. 522-528 (1988)。

Naofumi,Takagi: Proc.18th International Symposium on Fault-Tolerant Computing. 174-179 (1988)

Naofumi,Takagi：Proc.18th 国际容错计算研讨会。

Nagisa Ishiura: "Dynamic Two-Dimensional Parallel Simulation Technique for High-Speed Fault Simulation on a Vector Processor" Transactions of Information Processing Society of Japan, vol.29, no.5, pp.522-528, 1988.

Nagisa Ishiura：“矢量处理器上高速故障模拟的动态二维并行模拟技术”，日本信息处理学会会刊，第 29 卷，第 5 期，第 522-528 页，1988 年。

Naofumi Takagi: "Vector Algorithms for Generating Prime Implicants of Logic Functions" Proceedings of the Third International Conference on Supercomputing, vol.3, pp.281-287, 1988.

Naofumi Takagi：“生成逻辑函数素蕴涵的向量算法”第三届国际超级计算会议论文集，第 3 卷，第 281-287 页，1988 年。

Nagisa Ishiura: "Time-Symbolic Simulation for Accurate Timing Verification of Asynchronous Behavior of Logic Circuits" Proceedings of 26th ACM/IEEE Design Automation Conference, pp.497-502, 1989.

Nagisa Ishiura：“逻辑电路异步行为的精确时序验证的时间符号仿真”第 26 届 ACM/IEEE 设计自动化会议论文集，第 497-502 页，1989 年。