Reconfigurable logic and Multi-bit in-memory processing with ferroelectric memristors -ReLoFeMris

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Given the increasing demand for electronic devices in edge-computing applications and IoT, the energy consumption by data transmission from edge to cloud devices as well as the power consumption within the cloud will further increase, unless edge devices would become efficient enough to directly compute e.g. sensor date directly in places. Therefore, in order to realize an overall reduction of power consumption of the IT sector, and thus to facilitate the reduction of the world wide CO2 emission, it becomes increasingly important to develop electronic technologies that enable very efficient computing in mobile and edge devices. Therefore, novel computing paradigms that adopt non-volatile memory devices are of great interest. Especially for embedded devices it makes sense to execute simple logic operations where the data or the operands are located or are generated, namely in the memory or directly at sensor nodes. Near- and in-memory-computing is in principle an answer to the high energy costs of data transfer operations. The aspired project ReProFeMris pursuits the provision and practical implementation of future memristive ferroelectric technology and its application in future energy-efficient embedded in-memory processing architectures. The memristive ferroelectric technology that is to be exploited in the envisaged project is the ferroelectric tunneling junction (FTJ) that is one of the most power efficient technologies compared e.g. to classical ReRAM, STT-MRAM or PCM, that are under investigation at the present. Our project targets to exploit the unique features of ferroelectric memristive technology like MLC capability and reconfigurable logic for in memory arithmetic processing circuits. More specifically, we aim at the utilization of the ferroelectric tunneling junctions for the realization of non-volatile logic gates. Under consideration of the huge promises for extreme low-power operation that these devices possess, however, we target at leveraging the functionality of such concepts by overcoming the given limitations in limited MLC capability and low-current capability of these devices by means of circuit design. At the end of the first project period various basic arithmetic building blocks for extreme area-saving and energy-efficient reconfigurable memristive in-memory computing circuits as well as MLC feature exploiting circuits shall be realized in hardware and the results shall be published as a technical report which is public available via the web pages of NaMLab and FAU.